92HD90B0X5NLGXYAX8 IDT, 92HD90B0X5NLGXYAX8 Datasheet - Page 281

• Manufacturer Part Number: 92HD90B0X5NLGXYAX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of 92HD90B0X5NLGXYAX8

• Rohs: yes
• Part # Aliases: IDT92HD90B0X5NLGXYAX8

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
verb F78/778
verb F79/779
Register Address
Register Address
7.29.1.4. AIC3 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
7.29.1.5. PWRM Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
7:6
5
4
3
2:0
7
6
5
4
3
2
1
0
Bit
Bit
RSVD
SAEN
AUXSWAP
MCLKMS
MCLK[2:0]
RSVD
RSVD
RSVD
HPPWD
SPKRON
DMICPWD
MCLKOut
RSVD
Label
Label
RO
RW
RW
RW
RW
RO
RO
RO
RW
RW
RW
RW
RW
Type Default
Type
00
0
0
1
001
0
0
0
0
0
0
1
0
Default
281
Reserved
1 = Input enabled for I2S Secondary Audio
0 = Input disabled for Secondary Audio
Swap Left and Right Samples of Aux Audio Output.
0 = Left sample first in frame
1 = Right sample first in frame
MCLK master
0 = MCLK is an input
1 = MCLK is an output (not recommended in Aux Audio Mode
since 24/12MHz rates cant be supported and 112MHz internal
clock is imprecise but is useful for testing.)
MCLK rate
000 = 24MHz (HDA BitClk)
001 = 12MHz (HDA BitClk/2)
010 = 22.5792MHz
011 = 11.2896MHZ
100 = 5.6448MHZ
101 = 28.224MHz
110 = 14.112MHz
111 = 7.056MHz
DMIC powered down in Aux Audio Mode (including DAC)
Reserved
Reserved
Reserved
Headphone ports are forced off in Aux Audio Mode (including
charge pump)
BTL (port D) is forced on in Aux Audio Mode
MCLK Output Enabler
0 = MCLK Output is disabled in master mode
1 = MCLK is an output in master mode (input in slave mode))
Reserved
Description
Description
V 1.2 3/12
92HD98