92HD90B0X5NLGXYAX8 IDT, 92HD90B0X5NLGXYAX8 Datasheet - Page 68

• Manufacturer Part Number: 92HD90B0X5NLGXYAX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of 92HD90B0X5NLGXYAX8

• Rohs: yes
• Part # Aliases: IDT92HD90B0X5NLGXYAX8

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
Field Name
Control2
Control1
Control0
Field Name
Rsvd
W4
W3
W2
Reg
Get
Set
7.4.14. AFG (NID = 01h): GPIOWakeEn
Byte 4 (Bits 31:24)
Bits
2
Direction control for GPIO2: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
1
Direction control for GPIO1: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
0
Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
Bits
31:5
Reserved.
4
Wake enable for GPIO4: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
3
Wake enable for GPIO3: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
2
Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
Byte 3 (Bits 23:16)
R/W
RW
RW
RW
R/W
R
RW
RW
RW
F1800h
Default
0h
0h
0h
Default
00000000h
0h
0h
0h
63
Byte 2 (Bits 15:8)
Reset
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Byte 1 (Bits 7:0)
718h
V 1.2 3/12
92HD98