92HD90B0X5NLGXYAX8 IDT, 92HD90B0X5NLGXYAX8 Datasheet - Page 87

• Manufacturer Part Number: 92HD90B0X5NLGXYAX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of 92HD90B0X5NLGXYAX8

• Rohs: yes
• Part # Aliases: IDT92HD90B0X5NLGXYAX8

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
Field Name
Rsvd2
Detect
GainAdj
ConvertEn
DetectEn
Rsvd1
Gain
CntSel
Mode
Reg
Get
Set
7.4.31. AFG (NID = 01h): AnaBeep
Byte 4 (Bits 31:24)
Bits
31:14
Reserved.
13
0: no beep present; 1: beep present.
12:10
Analog PC Beep Gain in digital side 7h = -6dB, 6h = -12dB, 5h = -18dB, 4h = -24dB, 3h
= -30dB, 2h = -36dB, 1h = -42dB, 0h = -48dB.
9
Analog pc beep quantization enable (enabled only when both
""d2a_ana_pc_beep_det_en"" and ""d2a_ana_pc_beep_convert_en"" are 1).
8
Analog pc beep detection enable 0h = disable 1h = enable.
7:6
5:4
Analog PC Beep Gain: 0h = -24dB, 1h = -18dB, 2h = -12dB, 3h = -6dB.
3:2
Select counter delay.0h=64ms,1h = 128ms, 2h = 256ms, 3h = 512ms.
1:0
Analog PC Beep Mode:
00b = Always disabled
01b = Always enabled
1Xb = Enabled during HDA Link Reset only
Byte 3 (Bits 23:16)
R/W
R
R
RW
RW
RW
R
RW
RW
RW
FEE00h / FEE00h
Default
00000h
0h
3h
1h
1h
0h
3h
0h
2h
81
Byte 2 (Bits 15:8)
7EFh
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR
POR
POR
N/A (Hard-coded)
POR
POR
POR
Byte 1 (Bits 7:0)
7EEh
V 1.2 3/12
92HD98