92HD90B0X5NLGXYAX8 IDT, 92HD90B0X5NLGXYAX8 Datasheet - Page 38

• Manufacturer Part Number: 92HD90B0X5NLGXYAX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of 92HD90B0X5NLGXYAX8

• Rohs: yes
• Part # Aliases: IDT92HD90B0X5NLGXYAX8

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
SCLK[3:0]
1.In ‘Auto’ mode SCLK is referenced to the sample rate (SR[2:0] register bits) but in all other settigns the SCLK rate
1100
1101
1110
1111
is independent of the selected sample rate. Programming a sample rate that uses a different base rate from the
suggested sample rate may cause corruption of the audio stream.
It is possible to invert all clocks (shift, master, and LR clocks) as well as the Port F data input and
Port E data output.
The 92HD93 inverts the clocks and data by default.
Ports are enabled/disabled using the input / output enables defined in the pin widgets.
Aux Audio Mode will be supported and the CODEC will use the MCLK pin as an input in this mode. A
12MHz input will be accepted. (See the Aux Audio section for more information.)
In normal operation, the MCLK pin is an output by default but may be configured as an intput. 8 clock
frequencies are available: 22.5792MHz (512x 44.1K), 11.2896MHz (256x 44.1KHz), 5.6448MHz
(128x 44.1KHz), 28.224MHz (640x 44.1KHz), 14.112MHz (320x 44.1KHz), 7.056MHz (160x
44.1KHz), 24MHz (500x 48KHz), and 12MHz (250x 48KHz - default)
A “bit exact mode” is provided. In this mode, the output path will not alter the data from the DAC con-
verter widget (HD Audio stream data) sent to the I2S output port (Port E.) This means that there is no
sample rate conversion, rounding, filtering or other processing that will change the sample value.
Word length and sample rate are determined by the converter widget connected to the output port
and not by the I2S rate and word length configuration bits. The input port (if used) will have its rate
and word length converted to the requested rate of the ADC converter widget attached to the input
port. The input path may be bit exact if the DAC and ADC converter widgets are programmed to the
same rates and word lengths.
MCLK[2:0]
Frequency
000
001
010
100
101
011
110
111
(MHz)
7.056
3.528
1.764
Frequency
22.5792
11.2896
5.6448
28.224
14.112
(MHz)
7.056
PLL clock
24
12
divisor
16
32
64
PLL clock
divisor
Table 18. SCLK Frequency Selection
suggested
NA
NA
10
20
16
88.2KHz
44.1KHz
44.1KHz
5
4
8
sample
rate
Table 19. MCLK Frequency Selection
1
38
sample rate
88.2/48KHz
88.2/96KHz
suggested
88.2KHz
44.1KHz
44.1KHz
44.1KHz
96KHz
48KHz
clocks/fr
ame
80
80
40
HD Audio BitClk/2
HD Audio BitClk
reserved
Notes
Notes
V 1.2 3/12
92HD98