74LVC08APW-Q100,11 NXP Semiconductors, 74LVC08APW-Q100,11 Datasheet - Page 10

• Manufacturer Part Number: 74LVC08APW-Q100,11
• Description: Logic Gates
• Manufacturer: NXP Semiconductors

Specifications of 74LVC08APW-Q100,11

• Rohs: yes
• Product: AND
• Logic Family: 74LVC
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 /
• Propagation Delay Time: 10.4 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 50 mA
• Power Dissipation: 500 mW

NXP Semiconductors
Fig 10. Package outline SOT762-1 (DHVQFN14)
74LVC08A_Q100
Product data sheet
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT762-1
max.
A
1
(1)
terminal 1
index area
0.05
0.00
A 1
terminal 1
index area
E h
L
0.30
0.18
14
1
b
IEC
- - -
0.2
2
c
13
e
D
3.1
2.9
0
(1)
1.65
1.35
D h
e 1
D h
D
MO-241
JEDEC
All information provided in this document is subject to legal disclaimers.
E
2.6
2.4
(1)
b
REFERENCES
1.15
0.85
E h
9
Rev. 1 — 31 July 2012
6
0.5
e
7
8
JEITA
B
- - -
e
scale
w
v
2.5
e 1
2
M
M
A
E
C
C
0.5
0.3
A
L
B
0.1
v
0.05
w
y 1 C
A
A 1
0.05
74LVC08A-Q100
y
PROJECTION
EUROPEAN
5 mm
0.1
y 1
detail X
Quad 2-input AND gate
X
C
© NXP B.V. 2012. All rights reserved.
y
ISSUE DATE
02-10-17
03-01-27
c
SOT762-1
10 of 14