74LVC08APW-Q100,11 NXP Semiconductors, 74LVC08APW-Q100,11 Datasheet - Page 9

• Manufacturer Part Number: 74LVC08APW-Q100,11
• Description: Logic Gates
• Manufacturer: NXP Semiconductors

Specifications of 74LVC08APW-Q100,11

• Rohs: yes
• Product: AND
• Logic Family: 74LVC
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 /
• Propagation Delay Time: 10.4 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 50 mA
• Power Dissipation: 500 mW

NXP Semiconductors
Fig 9. Package outline SOT402-1 (TSSOP14)
74LVC08A_Q100
Product data sheet
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT402-1
max.
1.1
A
0.15
0.05
A
1
0.95
0.80
14
A
1
2
y
IEC
Z
0.25
pin 1 index
A
e
3
D
0.30
0.19
b
p
MO-153
All information provided in this document is subject to legal disclaimers.
JEDEC
0.2
0.1
c
b
p
8
7
REFERENCES
D
5.1
4.9
0
(1)
w
Rev. 1 — 31 July 2012
M
E
4.5
4.3
(2)
JEITA
scale
2.5
0.65
e
c
A
H
6.6
6.2
2
E
A
1
5 mm
L
1
0.75
0.50
L
H
p
E
E
detail X
0.4
0.3
Q
74LVC08A-Q100
L
L
PROJECTION
EUROPEAN
p
0.2
v
Q
A
(A )
0.13
Quad 2-input AND gate
3
w
X
θ
v
0.1
A
y
© NXP B.V. 2012. All rights reserved.
M
ISSUE DATE
A
99-12-27
03-02-18
0.72
0.38
Z
(1)
SOT402-1
8
0
θ
o
o
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