74LVC08APW-Q100,11 NXP Semiconductors, 74LVC08APW-Q100,11 Datasheet - Page 6

• Manufacturer Part Number: 74LVC08APW-Q100,11
• Description: Logic Gates
• Manufacturer: NXP Semiconductors

Specifications of 74LVC08APW-Q100,11

• Rohs: yes
• Product: AND
• Logic Family: 74LVC
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 /
• Propagation Delay Time: 10.4 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 50 mA
• Power Dissipation: 500 mW

NXP Semiconductors
10. Dynamic characteristics
Table 7.
Voltages are referenced to GND (ground = 0 V). For test circuit see
[1]
[2]
[3]
[4]
11. AC waveforms
74LVC08A_Q100
Product data sheet
Symbol Parameter
t
t
C
pd
sk(o)
Fig 6. The input nA, nB to output nY propagation delays
PD
Typical values are measured at T
t
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
C
P
f
C
V
N = number of inputs switching
(C
pd
i
D
CC
PD
= input frequency in MHz, f
L
is the same as t
= output load capacitance in pF
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts
 V
propagation delay
output skew time
power dissipation
capacitance
V
V
V
PD
M
M
OL
Dynamic characteristics
CC
 V
= 1.5 V at V
= 0.5  V
2
and V
 f
CC
o
2
) = sum of the outputs.
OH
 f
PLH
CC
i
are typical output voltage levels that occur with the output load.
 N + (C
CC
at V
and t
2.7 V
CC
PHL
o
< 2.7 V
= output frequency in MHz
L
.
 V
Conditions
nA, nB to nY; see
V
per gate; V
amb
CC
V
V
V
V
V
V
V
V
CC
nA, nB input
CC
CC
CC
CC
CC
CC
CC
CC
= 25 C and V
nY output
2
= 3.0 V to 3.6 V
 f
= 1.2 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
o
All information provided in this document is subject to legal disclaimers.
) where:
I
= GND to V
GND
V
V
OH
OL
V
I
CC
Figure 6
Rev. 1 — 31 July 2012
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
D
CC
in W).
V
M
V
M
t
PHL
[2]
[3]
[4]
Figure
Min
0.5
1.0
1.5
1.0
-
-
-
-
-
40 C to +85 C
7.
Typ
11.0
10.5
4.2
2.5
2.5
2.3
4.4
7.7
t
PLH
-
mna224
[1]
74LVC08A-Q100
Max
9.0
6.9
4.8
4.1
1.0
-
-
-
-
Quad 2-input AND gate
40 C to +125 C Unit
Min
0.5
1.0
1.5
1.0
-
-
-
-
© NXP B.V. 2012. All rights reserved.
Max
10.4
8.0
5.6
4.8
1.5
-
-
-
6 of 14
pF
pF
pF
ns
ns
ns
ns
ns
ns