74LVC08APW-Q100,11 NXP Semiconductors, 74LVC08APW-Q100,11 Datasheet - Page 8

• Manufacturer Part Number: 74LVC08APW-Q100,11
• Description: Logic Gates
• Manufacturer: NXP Semiconductors

Specifications of 74LVC08APW-Q100,11

• Rohs: yes
• Product: AND
• Logic Family: 74LVC
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 /
• Propagation Delay Time: 10.4 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 50 mA
• Power Dissipation: 500 mW

NXP Semiconductors
12. Package outline
Fig 8.
74LVC08A_Q100
Product data sheet
SO14: plastic small outline package; 14 leads; body width 3.9 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
inches
UNIT
mm
OUTLINE
VERSION
SOT108-1
Package outline SOT108-1 (SO14)
0.069
max.
1.75
A
0.010
0.004
0.25
0.10
A
14
1
1
Z
pin 1 index
y
0.057
0.049
1.45
1.25
A
2
076E06
IEC
0.01
0.25
e
A
3
0.019
0.014
0.49
0.36
b
p
D
0.0100
0.0075
0.25
0.19
MS-012
All information provided in this document is subject to legal disclaimers.
JEDEC
c
REFERENCES
8.75
8.55
0.35
0.34
D
(1)
0
Rev. 1 — 31 July 2012
0.16
0.15
E
4.0
3.8
b
(1)
p
8
7
JEITA
scale
1.27
0.05
2.5
e
w
M
c
0.244
0.228
H
6.2
5.8
E
A
2
0.041
5 mm
1.05
A
L
1
0.039
0.016
1.0
0.4
L
p
H
E
E
detail X
0.028
0.024
0.7
0.6
Q
74LVC08A-Q100
L
PROJECTION
L
EUROPEAN
0.25
0.01
p
Q
v
(A )
3
0.25
0.01
A
Quad 2-input AND gate
w
θ
A
0.004
0.1
v
y
X
© NXP B.V. 2012. All rights reserved.
M
ISSUE DATE
99-12-27
03-02-19
A
0.028
0.012
Z
0.7
0.3
(1)
SOT108-1
θ
8
0
o
o
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