74LVC08APW-Q100,11 NXP Semiconductors, 74LVC08APW-Q100,11 Datasheet - Page 2

• Manufacturer Part Number: 74LVC08APW-Q100,11
• Description: Logic Gates
• Manufacturer: NXP Semiconductors

Specifications of 74LVC08APW-Q100,11

• Rohs: yes
• Product: AND
• Logic Family: 74LVC
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 /
• Propagation Delay Time: 10.4 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 50 mA
• Power Dissipation: 500 mW

NXP Semiconductors
3. Ordering information
Table 1.
4. Functional diagram
74LVC08A_Q100
Product data sheet
Type number
74LVC08AD-Q100
74LVC08APW-Q100 40 C to +125 C
74LVC08ABQ-Q100 40 C to +125 C
Fig 1. Logic symbol
10
12
13
1
2
4
5
9
Ordering information
1A
1B
2A
2B
3A
3B
4A
4B
mna222
Package
Temperature range Name
40 C to +125 C
1Y
2Y
3Y
4Y
11
3
6
8
All information provided in this document is subject to legal disclaimers.
Fig 2. IEC logic symbol
SO14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
Rev. 1 — 31 July 2012
10
13
12
1
2
4
5
9
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
&
&
&
&
mna223
11
3
6
8
Fig 3. Logic diagram for one gate
A
B
74LVC08A-Q100
Quad 2-input AND gate
© NXP B.V. 2012. All rights reserved.
Version
SOT108-1
SOT402-1
SOT762-1
mna221
2 of 14
Y