DS3172N Maxim Integrated, DS3172N Datasheet - Page 144

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

12.4 BERT
12.4.1 BERT Register Map
The BERT utilizes 12 registers. Note: The BERT tegisters will be cleared when GL.CR1.RSTDP or
PORT.CR1.RSTDP or PORT.CR1.PD is set.
Table 12-14. BERT Register Map
12.4.2 BERT Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Performance Monitoring Update Mode (PMUM) – When 0, a performance monitoring update is initiated by
the LPMU register bit. When 1, a performance monitoring update is initiated by the global or port PMU register bit.
Note: If the LPMU bit or the global or port PMU bit is one, changing the state of this bit may cause a performance
monitoring update to occur.
Bit 6: Local Performance Monitoring Update (LPMU) – This bit causes a performance monitoring update to be
initiated if local performance monitoring update is enabled (PMUM = 0). A 0 to 1 transition causes the performance
monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance
monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit
goes high, an update might not be performed. This bit has no affect when PMUM=1.
(0,2,4,6)6Ah
(0,2,4,6)6Ch
(0,2,4,6)6Eh
(0,2,4,6)7Ah
(0,2,4,6)7Ch
(0,2,4,6)7Eh
(0,2,4,6)60h
(0,2,4,6)62h
(0,2,4,6)64h
(0,2,4,6)66h
(0,2,4,6)68h
(0,2,4,6)70h
(0,2,4,6)72h
(0,2,4,6)74h
(0,2,4,6)76h
(0,2,4,6)78h
Address
PMUM
15
--
0
7
0
BERT.CR
BERT.PCR
BERT.SPR1
BERT.SPR2
BERT.TEICR
--
BERT.SR
BERT.SRL
BERT.SRIE
--
BERT.RBECR1
BERT.RBECR2
BERT.RBCR1
BERT.RBCR2
--
--
Register
LPMU
14
--
0
6
0
BERT.CR
BERT Control Register
(0,2,4,6)60h
RNPL
BERT Control Register
BERT Pattern Configuration Register
BERT Seed/Pattern Register #1
BERT Seed/Pattern Register #2
BERT Transmit Error Insertion Control Register
Unused
BERT Status Register
BERT Status Register Latched
BERT Status Register Interrupt Enable
Unused
BERT Receive Bit Error Count Register #1
BERT Receive Bit Error Count Register #2
BERT Receive Bit Count Register #1
BERT Receive Bit Count Register #2
Unused
Unused
13
Register Description
--
0
5
0
RPIC
12
--
0
0
4
144
MPR
11
--
0
3
0
APRD
10
--
0
2
0
TNPL
--
9
0
1
0
TPIC
--
8
0
0
0