DS3172N Maxim Integrated, DS3172N Datasheet - Page 52
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DS3172N
Manufacturer Part Number
DS3172N
Description
Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
Manufacturer
Maxim Integrated
Datasheet
1.DS3171.pdf
(234 pages)
Specifications of DS3172N
Part # Aliases
90-31720-N00
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Figure 10-1. Interrupt Structure
Figure 10-1
enable a particular interrupt. Each block has a Status Register Interrupt Enable register that must be set in order to
enable an interrupt. The next step is to unmask the interrupt at the port level, on a per port basis. This is controlled
in the Global Interrupt Status Register Interrupt Enable register (GL.ISRIE). Now the device is ready to drive the
INT pin low when a particular status bit gets set.
For example, in order to enable DS3 Out of Frame interrupts on Port 2, the following registers would need to be
written:
Register bit
T3.RSRIE1.OOFIE
GL.ISRIE.PISRIE2
The following status registers bits will be set upon reception of OOF on Port 2:
Register bit
T3.RSRL1.OOFL
PORT.ISR.FMSR
GL.ISR.PISR2
10.2 Clocks
10.2.1 Line Clock Modes
10.2.1.1 Loop Timing Enabled
When loop timing is enabled (PORT.CR3.LOOPT), the transmit clock source is the same as the receive clock
source. The TCLKIn pins are not used as a clock source. Because loop timing is enabled, the loopback functions
(LLB, PLB and DLB) do not cause the clock sources to switch when they are activated. The transmit and receive
BLOCK LATCHED
STATUS and
INTERRUPT
ENABLE
REGISTERS
SRIE bit
SRIE bit
SRIE bit
SRL bit
SRL bit
SRL bit
not only tells the user how to determine which event caused the interrupt, it also tells the user how to
Address
0x2BC
0x010
Address
0x2B8
0x250
0x010
PORT INTERRUPT
STATUS
REGISTER
PORT.ISR bit
Value Written
0x0020
Value Read
0x0002
0x0001
0x0020
0x0002
GLOBAL
INTERRUPT
STATUS REGISTER
and INTERRUPT
ENABLE REGISTER
GL.ISR.PISRn
52
GL.ISRIE.
PISRIEn
Note
DS3 Out of Frame on Port 2
Framer Block Interrupt Active, Port 2
Port 2 Interrupt Active
Note
Unmask OOF interrupt on Port 2
Unmask Port 2 interrupts
INTERRUPTS
PORT
INTERRUPTS
GLOBAL
INT
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