DS3172N Maxim Integrated, DS3172N Datasheet - Page 96

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

10.7 HDLC Overhead Controller
10.7.1 General Description
The DS3174,3,2,1 devices contain built-in HDLC controllers (one per port) with 256 byte FIFOs for
insertion/extraction of DS3 PMDL, G.751 Sn bit and G.832 NR/GC bytes.
The HDLC Overhead Controller demaps HDLC overhead packets from the DS3/E3 data stream in the receive
direction and maps HDLC packets into the DS3/E3 data stream in the transmit direction.
The receive direction performs packet processing and stores the packet data in the FIFO. It removes packet data
from the FIFO and outputs the packet data to the microprocessor via the register interface.
The transmit direction inputs the packet data from the microprocessor via the register interface and stores the
packet data in the FIFO. It removes the packet data from the FIFO and performs packet processing.
The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB
last. The bits in a byte in an incoming signal are numbered in the order they are received, 1 (MSB) to 8 (LSB).
However, when a byte is stored in a register, the MSB is stored in the lowest numbered bit (0), and the LSB is
stored in the highest numbered bit (7). This is to differentiate between a byte in a register and the corresponding
byte in a signal. See
Figure 10-20. HDLC Controller Block Diagram
10.7.2 Features
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Programmable inter-frame fill – The inter-frame fill between packets can be all 1’s or flags.
Programmable FCS generation/monitoring – An FCS-16 can be generated and appended to the end of the
packet, and the FCS can be checked and removed from the end of the packet.
Programmable bit reordering – The packet data can be can be output MSB first or LSB first from the FIFO.
Programmable data inversion – The packet data can be inverted immediately after packet processing on the
transmit, and immediately before packet processing on the receive.
Fully independent transmit and receive paths
Fully independent Line side and register interface timing – The data storage can be read from or written to
via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to
via the line side while all microprocessor interface clocks and signals are inactive.
Clock Rate
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Figure 10-20
Decoder
Encoder
B3ZS/
HDB3
HDB3
B3ZS/
TUA1
TAIS
for the location of HDLC controllers within the DS317x devices.
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
DS3 / E3
Receive
Framer
Transmit
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
96
RX BERT
TX BERT
Microprocessor
Interface