DS3172N Maxim Integrated, DS3172N Datasheet - Page 178

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the
transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to
be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and
this bit transitions more than once between error insertion opportunities, only one error will be inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.
12.9.2 Receive DS3 Register Map
The receive DS3 utilizes eleven registers. Two registers are shared for C-Bit and M23 DS3 modes. The M23 DS3
mode does not use the RFEBER or RCPECR count registers.
Table 12-24. Receive DS3 Framer Register Map
(1,3,5,7)2Ch
(1,3,5,7)3Ch
12.9.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 14: C-bit Overhead Masking Disable (COVHD) – When 0, the C-bit positions will be marked as overhead
(RDENn=0). When 1, the C-bit positions will be marked as data (RDENn=1). This bit is ignored in C-bit DS3 mode
or when the ROMD bit is set to one.
(1,3,5,7)2Ah
(1,3,5,7)2Eh
(1,3,5,7)3Ah
(1,3,5,7)3Eh
(1,3,5,7)20h
(1,3,5,7)22h
(1,3,5,7)24h
(1,3,5,7)26h
(1,3,5,7)28h
(1,3,5,7)30h
(1,3,5,7)32h
(1,3,5,7)34h
(1,3,5,7)36h
(1,3,5,7)38h
Address
Reserved
RAILE
T3.RCR
T3.RSR1
T3.RSR2
T3.RSRL1
T3.RSRL2
T3.RSRIE1
T3.RSRIE2
T3.RFECR
T3.RPECR
T3.RFBECR
T3.RCPECR
15
0
7
0
Register
--
--
--
--
--
COVHD
RAILD
14
0
6
0
T3 Receive Control Register
Reserved
T3 Receive Status Register #1
T3 Receive Status Register #2
T3 Receive Status Register Latched #1
T3 Receive Status Register Latched #2
T3 Receive Status Register Interrupt Enable #1
T3 Receive Status Register Interrupt Enable #2
Reserved
Reserved
T3 Receive Framing Error Count Register
T3 Receive P-bit Parity Error Count Register
T3 Receive Far-End Block Error Count Register
T3 Receive C-bit Parity Error Count Register
Unused
Unused
Register Description
T3.RCR
T3 Receive Control Register
(1,3,5,7)20h
RAIOD
MAOD
13
0
5
0
MDAISI
RAIAD
12
0
0
4
178
ROMD
AAISD
11
0
3
0
ECC
LIP1
10
0
2
0
FECC1
LIP0
9
0
1
0
FRSYNC
FECC0
8
0
0
0