DS3172N Maxim Integrated, DS3172N Datasheet - Page 185

• Manufacturer Part Number: DS3172N
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172N

• Part # Aliases: 90-31720-N00

Bit 2: Far-End Block Error Count Interrupt Enable (FBECIE) – This bit enables an interrupt if the FBECL bit is
set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: P-bit Parity Error Count Interrupt Enable (PECIE) – This bit enables an interrupt if the PECL bit is set and
the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Framing Error Count (FE[15:0]) – These sixteen bits indicate the number of framing error events on
the incoming DS3 data stream. This register is updated via the PMU signal (see Section 10.4.5).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: P-bit Parity Error Count (PE[15:0]) – These sixteen bits indicate the number of P-bit parity errors
detected on the incoming DS3 data stream. This register is updated via the PMU signal (see Section 10.4.5).
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
FE15
PE15
FE7
PE7
15
15
0
7
0
0
7
0
FE14
PE14
PE6
FE6
14
14
0
6
0
0
6
0
T3.RFECR
T3 Receive Framing Error Count Register
(1,3,5,7)34h
T3.RPECR
T3 Receive P-bit Parity Error Count Register
(1,3,5,7)36h
PE13
FE13
PE5
FE5
13
13
0
5
0
0
5
0
FE12
PE12
FE4
PE4
12
12
0
0
0
0
4
4
185
PE11
FE11
PE3
FE3
11
11
0
3
0
0
3
0
FE10
PE10
FE2
PE2
10
10
0
2
0
0
2
0
FE9
FE1
PE9
PE1
9
0
1
0
9
0
1
0
PE8
PE0
FE8
FE0
8
0
0
0
8
0
0
0