MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 108

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
The maximal accuracy of UP/DOWN edge of controls is:
108
1
2
IP5o
IP13o Offset of VSYNC
IP8o
IP9o
ID
Display interface clock period immediate value.
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
Offset of IPP_DISP_CLK
Offset of HSYNC
Offset of DRDY
Table 68. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
Tdicp
Parameter
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
=
⎧
⎪
⎪
⎨
⎪
⎪
⎩
T
diclk
T diclk
⎛
⎝
floor
×
DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
Symbol
DISP_CLK_PERIOD
--------------------------------------------------- -
Todrdy
Todicp
DI_CLK_PERIOD
Tohs
Tovs
Tdicp
Accuracy
=
DISP_CLK_OFFSET
T
VSYNC_OFFSET
HSYNC_OFFSET
diclk
DRDY_OFFSET
=
,
×
×
×
×
×
(
Value
0.5
Tdiclk
Tdiclk
Tdiclk
Tdiclk
DISP_CLK_PERIOD
----------------------------------------------------
+
DI_CLK_PERIOD
0.5
×
T
±
diclk
0.5
⎞
⎠
) 0.62ns
,
±
for fractional DISP_CLK_PERIOD
DISP_CLK_OFFSET—offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK
(0.5 DI_CLK Resolution).
Defined by DISP_CLK counter
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK
(0.5 DI_CLK Resolution). The
VSYNC_OFFSET should be built by
suitable DI’s counter.
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK
(0.5 DI_CLK Resolution). The
HSYNC_OFFSET should be built by
suitable DI’s counter.
DRDY_OFFSET—offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK
(0.5 DI_CLK Resolution).
The DRDY_OFFSET should be built by
suitable DI’s counter.
for integer
DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
----------------------------------------------------
DI_CLK_PERIOD
Description
×
×
2
2
Freescale Semiconductor
×
×
2
2
Unit
ns
ns
ns
ns