MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 88

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
4.11.5.1.4
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 48
shown in the figure.
4.11.5.2 RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the CRS_DV in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET_RX_ER.
88
M10
M11
M12
M13
M14
M15
ID
ENET_MDIO (output)
ENET_MDC (output)
ENET_MDIO (input)
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
ENET_MDC pulse width low
shows MII asynchronous input timings.
MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Figure 48. MII Serial Management Channel Timing Diagram
Table 59. MII Serial Management Channel Timing
Characteristic
M12
M13
Table 59
M14
describes the timing parameters (M10–M15)
Min.
40%
40%
M10
18
—
0
0
M11
M15
Max.
60%
60%
—
—
—
5
Freescale Semiconductor
ENET_MDC period
ENET_MDC period
Unit
ns
ns
ns
ns