MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 7

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers:
The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted
multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance
at low power consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators:
Security functions are enabled and accelerated by the following hardware:
Freescale Semiconductor
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— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
— Two Controller Area Network (FlexCAN), 1 Mbps each
— Two Watchdog timers (WDOG)
— Audio MUX (AUDMUX)
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Support DVFS techniques for low power modes
Use SW State Retention and Power Gating for ARM and MPE
Support various levels of system power modes
Use flexible clock gating control scheme
VPU—Video Processing Unit
IPUv3H—Image Processing Unit version 3H
GPU3Dv5—3D Graphics Processing Unit (OpenGL ES 2.0) version 5
GPU2Dv2—2D Graphics Processing Unit (BitBlt)
PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to
support the EPD display applications.
ASRC—Asynchronous Sample Rate Converter
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash
engines, 16 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified).
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Introduction
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