MCIMX503EVM8B Freescale Semiconductor, MCIMX503EVM8B Datasheet - Page 32

• Manufacturer Part Number: MCIMX503EVM8B
• Description: Processors - Application Specialized Codex Rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX503EVM8B

• Rohs: yes
• Core: ARM Cortex A8
• Processor Series: i.MX50
• Data Bus Width: 32 bit
• Operating Supply Voltage: 0.75 V to 1.275 V
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Memory Type: L1/L2 Cache, ROM, SRAM

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2
3
4
5
6
Electrical Characteristics
1
2
4.3.2
The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The
Jedec LPDDR2 specification (JESD209_2B) supersedes any specification in this document. The
parameters in
32
High-level output voltage
Low-level output voltage
Output min source current
Output min sink current
Input reference voltage
DC input high voltage (data pins)
DC input low voltage (data pins)
DC input voltage
DC differential input voltage
Termination voltage
Input current
Tri-state I/O supply current
Tri-state 2.5V predrivers supply
current
Tri-state core supply current
Input current (100 KΩ PD)
External pull-up / pull-down
resistor required to overdrive
internal keeper
ovdd=1.7 V; Vout=1.42 V. (Vout-ovdd)/Ioh must be less than 21 Ω for values of Vout between ovdd and ovdd-0.28 V.
ovdd=1.7 V; Vout=280 mV. Vout/Iol must be less than 21 Ω for values of Vout between 0 V and 280 mV.
Vin(dc) specifies the allowable dc excursion of each differential input.
Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “pure” input level and Vcp is the
“complementary” input level. the minimum value is equal to Vih(dc) - Vil(dc).
Vtt is expected to track ovdd/2.
Typ condition: typ model, 1.8 V, and 25 °C. Max condition: BCS model, 1.9 V, and 125 °C. Min condition: WCS model, 1.7 V,
and -40 °C.
DC Electrical Characteristics
DC Electrical Characteristics
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. VIL and VIH do not apply
when hysteresis is enabled.
Hysteresis of 250 mV is guaranteed overall operating conditions when hysteresis is enabled.
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6
DDR2 I/O DC Parameters
(no pull-up/down)
Table 18
3
(clk pins)
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2
1
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4
are guaranteed per the operating ranges in
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i.MX50 Applications Processors for Consumer Products, Rev. 4
Table 17. GPIO DC Electrical Characteristics (continued)
Table 18. DDR2 DC Electrical Characteristics
Icc-vdd2p5
Symbol
Icc-ovdd
Vihd(dc)
Symbol
Vild(dc)
Icc-vddi
Ioh(dc)
Vin(dc)
Vid(dc)
Iol(dc)
Rext
IIN
Vref
Voh
Vol
Vtt
Iin
VI = ovdd or 0
VI = ovdd or 0
VI = ovdd or 0
Conditions
Test Conditions
VI=ovdd
VI = 0
Test
VI=OVDD
—
—
—
—
—
—
—
—
—
—
VI = 0
—
Vref+0.125
0.49*ovdd
Vref-0.04
0.9*ovdd
0.25
MIN
-7.5
-0.3
-0.3
7.5
—
—
—
—
—
Table
MIN
—
—
11, unless otherwise noted.
0.5*ovdd
0.07
TYP
Vref
2.3
6.4
3.1
—
—
—
—
—
—
—
—
2
Typ
—
—
Freescale Semiconductor
Vref-0.125
0.51*ovdd
Vref+0.04
ovdd+0.3
ovdd+0.3
ovdd+0.6
0.1*ovdd
MAX
MAX
0.25
360
480
750
720
—
—
—
36
47
5
Units
Units
KΩ
μA
mA
mA
nA
nA
nA
nA
—
—
V
V
V
V
V
V