MCIMX6D4AVT10ACR Freescale Semiconductor, MCIMX6D4AVT10ACR Datasheet - Page 102

• Manufacturer Part Number: MCIMX6D4AVT10ACR
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D4AVT10ACR

• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counter system can be found in the IPU
chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).
4.11.10.5.2 Asynchronous Controls
The asynchronous control is a data-oriented signal that changes its value with an output data according to
additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
4.11.10.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
4.11.10.6.1 IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface:
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point. The data bus of the synchronous interface is output direction only.
4.11.10.6.2 LCD Interface Functional Description
Figure 68
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
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The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.
The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any other data-oriented signal to display.
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
VSYNC—Vertical synchronization
DRDY—Active data
DI_CLK internal DI clock is used for calculation of other controls.
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data on the bus, a
new internal start (local start point) is generated. The signal generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
NOTE
Freescale Semiconductor