MCIMX6D4AVT10ACR Freescale Semiconductor, MCIMX6D4AVT10ACR Datasheet - Page 49

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MCIMX6D4AVT10ACR

Manufacturer Part Number
MCIMX6D4AVT10ACR
Description
Processors - Application Specialized i.MX6D
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX6D4AVT10ACR

Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
4.9
This section contains the timing and electrical parameters for the modules in each i.MX 6Dual/6Quad
processor.
4.9.1
Figure 10
4.9.2
Figure 11
Freescale Semiconductor
CC1 Duration of SRC_POR_B to be qualified as valid (input slope <= 5 ns)
ID
CC3
ID
Duration of WDOG1_B Assertion
System Modules Timing
shows the WDOG reset timing and
shows the reset timing and
Reset Timing Parameters
WDOG Reset Timing Parameters
XTALOSC_RTC_XTALI is approximately 32 kHz.
XTALOSC_RTC_XTALI cycle is one period or approximately 30 s.
WDOG1_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
WDOG1_B
(Output)
Parameter
SRC_POR_B
(Input)
Parameter
Table 39. WDOG1_B Timing Parameters
Figure 11. WDOG1_B Timing Diagram
Table 38. Reset Timing Parameters
Figure 10. Reset Timing Diagram
Table 38
Table 39
lists the timing parameters.
NOTE
NOTE
Min
1
lists the timing parameters.
CC3
CC1
Max
Min Max
1
XTALOSC_RTC_ XTALI cycle
XTALOSC_RTC_ XTALI cycle
Electrical Characteristics
Unit
Unit
49

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