MCIMX6D4AVT10ACR Freescale Semiconductor, MCIMX6D4AVT10ACR Datasheet - Page 120

• Manufacturer Part Number: MCIMX6D4AVT10ACR
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D4AVT10ACR

• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
1
2
3
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed in
Table 80
delay, setup, and hold times.
120
1
2
3
Cycle-to-cycle system jitter
Transmitter MLB_SIG_P/_N
(MLB_DATA_P/_N) output valid from transition
of MLB_CLK_P/_N (low-to-high)
Disable turnaround time from transition of
MLB_CLK_P/_N (low-to-high)
MLB_CLK Operating Frequency
MLB_CLK rise time
MLB_CLK fall time
MLB_CLK low time
MLB_CLK high time
MLB_SIG/MLB_DATA receiver input valid to
MLB_CLK falling
MLB_SIG/MLB_DATA receiver input hold
from MLB_CLK low
MLB_SIG/MLB_DATA output high
impedance from MLB_CLK low
Bus Hold from MLB_CLK low
The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLB_CLK.
MLB_CLK low/high time includes the pulse width variation.
The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the
final driven bit on the line must remain on the bus for t
load capacitance listed.
The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLB_CLK.
MLB_CLK low/high time includes the pulse width variation.
The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the
final driven bit on the line must remain on the bus for t
load capacitance listed.
lists the MediaLB 6-pin interface timing characteristics, and
Parameter
Parameter
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
1
1
Table 80. MLB 6-Pin Interface Timing Parameters
Table 79. MLB 1024 Fs Timing Parameters
Symbol
t
t
t
t
t
t
t
t
dhmcf
f
dsmcf
mcfdz
Symbol
mckh
mdzh
mckr
mckf
mckl
mck
t
t
delay
t
jitter
phz
mdzh
mdzh
. Therefore, coupling must be minimized while meeting the maximum
. Therefore, coupling must be minimized while meeting the maximum
45.056
t
Min
mdzh
6.1
9.3
—
—
1
0
2
Min
0.6
0.6
—
51.2
Max
t
mckl
—
—
—
—
—
1
1
Max
600
1.3
3.5
Table
Figure 88
79; unless otherwise noted.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ps
ns
ns
shows the MLB 6-pin
1024xfs at 44.0 kHz
1024xfs at 50.0 kHz
V
V
IL
IH
Freescale Semiconductor
TO V
TO V
Comment
IH
IL
Comment
(see
(see
—
—
—
—
—
—
—
2
3
)
)