MCIMX6D4AVT10ACR Freescale Semiconductor, MCIMX6D4AVT10ACR Datasheet - Page 82

• Manufacturer Part Number: MCIMX6D4AVT10ACR
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D4AVT10ACR

• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

1
2
3
4
Electrical Characteristics
4.11.4.2
Figure 46
Be aware that only SDx_DATAx is sampled on both edges of the clock (not applicable to SD_CMD).
82
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0
clock frequency can be any value between 0
In normal (full) speed mode for MMC card, clock frequency can be any value between 0
frequency can be any value between 0
SD7
SD8
ID
SD1
SD1
SD2
SD3
SD4
ID
eSDHC Input Setup Time
eSDHC Input Hold Time
depicts the timing of eMMC4.4/4.41.
eMMC4.4/4.41 (Dual Data Rate) eSDHCv3 AC Timing
Clock Frequency (EMMC4.4 DDR)
Clock Frequency (SD3.0 DDR)
uSDHC Output Delay
uSDHC Input Setup Time
uSDHC Input Hold Time
Output from eSDHCv3 to card
Input from card to eSDHCv3
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
uSDHC Output / Card Inputs SD_CMD, SD_DATAx (Reference to SD_CLK)
uSDHC Input / Card Outputs SD_CMD, SD_DATAx (Reference to SD_CLK)
eSDHC Input/Card Outputs SD_CMD, SD_DATAx (Reference to SDx_CLK)
Table 55. SD/eMMC4.3 Interface Timing Specification (continued)
SDx_DATA[7:0]
SDx_DATA[7:0]
Table 56. eMMC4.4/4.41 Interface Timing Specification
Parameter
4
SDx_CLK
Parameter
–
52 MHz.
Figure 46. eMMC4.4/4.41 Timing
–
50 MHz.
SD2
Card Input Clock
Table 56
SD3
lists the eMMC4.4/4.41 timing characteristics.
Symbols
t
t
f
f
ISU
t
OD
PP
PP
IH
Symbols
SD4
SD2
t
ISU
t
IH
SD1
Min
2.5
2.6
1.5
0
0
–
20 MHz. In high-speed mode, clock
Min
2.5
1.5
–
25 MHz. In high-speed mode,
Max
7.1
52
50
—
—
Freescale Semiconductor
......
......
Max
—
—
MHz
MHz
Unit
ns
ns
ns
Unit
ns
ns