C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 125

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

18.5.1. FIFO Split Mode
The FIFO space for Endpoints1-2 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint1 FIFO is configured
for Split Mode, the upper 64 bytes (0x0480 to 0x04BF) are used by Endpoint1 IN and the lower 64 bytes
(0x0440 to 0x047F) are used by Endpoint1 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see SFR Definition 18.13).
18.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-2 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for
Endpoints1-2. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN
Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for
the entire endpoint FIFO. See Table 18.3 for a list of maximum packet sizes for each FIFO configuration.
0x04C0
0x04BF
0x04FF
0x03FF
0x043F
0x0440
0x0400
0x0000
(1024 bytes)
User XRAM
(128 bytes)
Endpoint0
Endpoint1
Endpoint2
(64 bytes)
(64 bytes)
Figure 18.3. USB FIFO Allocation
C8051T622/3 and C8051T326/7
Rev. 1.1
USB Clock Dom ain
System Clock Dom ain
IN, O UT, or both (Split
Configurable as
M ode)
125