C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 126

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051T622/3 and C8051T326/7
Table 18.3. FIFO Configurations
18.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
USB Register Definition 18.6. FIFOn: USB0 Endpoint FIFO Access
USB Register Address = 0x20-0x22
126
Name
Reset
7:0
Bit
Type
Bit
Endpoint
Number
FIFODATA[7:0] Endpoint FIFO Access Bits.
0
1
2
Name
7
0
Split Mode
Enabled?
N/A
USB Addresses 0x20-0x22 provide access to the 4 pairs of endpoint FIFOs:
0x20: Endpoint 0
0x21: Endpoint 1
0x22: Endpoint 2
Writing to the FIFO address loads data into the IN FIFO for the corresponding
endpoint. Reading from the FIFO address unloads data from the OUT FIFO for
the corresponding endpoint.
N
Y
N
Y
6
0
5
0
(Double Buffer Disabled /
Maximum IN Packet Size
Enabled)
Rev. 1.1
64 / 32
32 / 16
FIFODATA[7:0]
4
0
R/W
Function
3
0
128 / 64
64/ 32
64
Maximum OUT Packet Size
(Double Buffer Disabled /
2
0
Enabled)
64 / 32
32 / 16
1
0
0
0