C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 13

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051T622/3 and C8051T326/7
SFR Definition 17.15. P1SKIP: Port 1 Skip ................................................................. 114
SFR Definition 17.16. P2: Port 2 ................................................................................. 114
SFR Definition 17.17. P2MDOUT: Port 2 Output Mode .............................................. 115
SFR Definition 18.1. USB0XCN: USB0 Transceiver Control ...................................... 118
SFR Definition 18.2. USB0ADR: USB0 Indirect Address ........................................... 120
SFR Definition 18.3. USB0DAT: USB0 Data .............................................................. 121
USB Register Definition 18.4. INDEX: USB0 Endpoint Index ..................................... 123
USB Register Definition 18.5. CLKREC: Clock Recovery Control .............................. 124
USB Register Definition 18.6. FIFOn: USB0 Endpoint FIFO Access .......................... 126
USB Register Definition 18.7. FADDR: USB0 Function Address ............................... 127
USB Register Definition 18.8. POWER: USB0 Power ................................................ 129
USB Register Definition 18.9. FRAMEL: USB0 Frame Number Low ......................... 130
USB Register Definition 18.10. FRAMEH: USB0 Frame Number High ...................... 130
USB Register Definition 18.11. IN1INT: USB0 IN Endpoint Interrupt ......................... 131
USB Register Definition 18.12. OUT1INT: USB0 OUT Endpoint Interrupt ................. 132
USB Register Definition 18.13. CMINT: USB0 Common Interrupt ............................. 133
USB Register Definition 18.14. IN1IE: USB0 IN Endpoint Interrupt Enable ............... 134
USB Register Definition 18.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable ....... 135
USB Register Definition 18.16. CMIE: USB0 Common Interrupt Enable .................... 136
USB Register Definition 18.17. E0CSR: USB0 Endpoint0 Control ............................. 139
USB Register Definition 18.18. E0CNT: USB0 Endpoint0 Data Count ....................... 140
USB Register Definition 18.19. EENABLE: USB0 Endpoint Enable ........................... 141
USB Register Definition 18.20. EINCSRL: USB0 IN Endpoint Control Low ............... 143
USB Register Definition 18.21. EINCSRH: USB0 IN Endpoint Control High .............. 144
USB Register Definition 18.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 146
USB Register Definition 18.23. EOUTCSRH: USB0 OUT Endpoint Control 
High Byte ................................................................... 147
USB Register Definition 18.24. EOUTCNTL: USB0 OUT Endpoint Count Low ......... 147
USB Register Definition 18.25. EOUTCNTH: USB0 OUT Endpoint Count High ........ 148
SFR Definition 19.1. SMB0CF: SMBus Clock/Configuration ...................................... 155
SFR Definition 19.2. SMB0CN: SMBus Control .......................................................... 157
SFR Definition 19.3. SMB0ADR: SMBus Slave Address ............................................ 159
SFR Definition 19.4. SMB0ADM: SMBus Slave Address Mask .................................. 160
SFR Definition 19.5. SMB0DAT: SMBus Data ............................................................ 161
SFR Definition 20.1. SCON0: Serial Port 0 Control .................................................... 176
SFR Definition 20.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 177
SFR Definition 21.1. SCON1: UART1 Control ............................................................ 184
SFR Definition 21.2. SMOD1: UART1 Mode .............................................................. 185
SFR Definition 21.3. SBUF1: UART1 Data Buffer ...................................................... 186
SFR Definition 21.4. SBCON1: UART1 Baud Rate Generator Control ...................... 187
SFR Definition 21.5. SBRLH1: UART1 Baud Rate Generator High Byte ................... 187
SFR Definition 21.6. SBRLL1: UART1 Baud Rate Generator Low Byte ..................... 188
SFR Definition 22.1. SPI0CFG: SPI0 Configuration ................................................... 196
SFR Definition 22.2. SPI0CN: SPI0 Control ............................................................... 197
SFR Definition 22.3. SPI0CKR: SPI0 Clock Rate ....................................................... 198
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