MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet
MT46V32M4TG-6T:D TR
Specifications of MT46V32M4TG-6T:D TR
Related parts for MT46V32M4TG-6T:D TR
MT46V32M4TG-6T:D TR Summary of contents
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Double Data Rate (DDR) SDRAM MT46V32M4 – 8 Meg banks MT46V16M8 – 4 Meg banks MT46V8M16 – 2 Meg banks For the latest data sheet revisions, please refer ...
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... Not all speeds and all configurations are available in all packages. General Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con- taining 134,217,728 bits internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation ...
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... A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The 128Mb DDR SDRAM operates from a differential clock (CK and CK#) ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 128Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... BA0, BA1 REGISTER 2 11 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN BANK3 BANK2 BANK1 BANK0 ROW- 12 ADDRESS ROW- BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 1,024 x 8) DECODER SENSE AMPLIFIERS 8192 I/O GATING 2 DM MASK LOGIC BANK CONTROL LOGIC 1024 (x8) COLUMN DECODER ...
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... BA0, BA1 REGISTER 2 10 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN BANK3 BANK2 BANK1 ROW- BANK0 12 ROW- ADDRESS BANK0 MUX ADDRESS MEMORY 4096 LATCH ARRAY & (4,096 x 512 x 16) DECODER SENSE AMPLIFIERS 8192 I/O GATING 2 DM MASK LOGIC BANK CONTROL LOGIC 512 (x16) COLUMN ...
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... A0-A11, ADDRESS 14 BA0, BA1 REGISTER 2 9 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN BANK3 BANK2 BANK1 12 BANK0 12 ROW- BANK0 ADDRESS MEMORY 4096 LATCH ARRAY & (4,096 x 256 x 32) DECODER SENSE AMPLIFIERS 8192 I/O GATING DM MASK LOGIC BANK CONTROL LOGIC 256 (x32) COLUMN DECODER COLUMN- ...
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... Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE A11 command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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Table 4: Ball/Pin Descriptions (Continued) FBGA TSOP Numbers Numbers Symbol DQ0–DQ2 7, 8, 10, DQ3–DQ5 11, 13, 54, DQ6–DQ8 56, 57, 59, DQ9–DQ11 60, 62, 63, DQ12–DQ14 65 DQ15 14, 17, 25, 42, 43, 53 A8, B7, ...
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Figure 5: Pin Assignment (Top View) 66-pin TSOP DQ0 DQ1 DNU ...
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Figure 6: Ball Assignment (Top View) 60-Ball FBGA 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN Ball/Pin Descriptions and Assignments x4 (Top View ...
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... Functional Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con- taining 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quad- bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation ...
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Figure 7: Mode Register Definition * M13 and M12 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN BA1 BA0 A11 A10 A9 A8 ...
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Table 6: Burst Definition Burst Length Starting Column Address Notes: 1. Whenever a boundary of the block is reached within a given sequence above, the fol- ...
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Figure 8: CAS Latency COMMAND DQS COMMAND DQS COMMAND Table 7: CAS Latency (CL) Speed 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev CK# CK READ NOP CK# CK READ NOP CL = ...
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Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER ...
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Figure 9: Extended Mode Register Definition BA1 BA0 E11 E10 0 0 – – Notes: 1. E13 and E12 (BA1 and BA0) must be “0, 1” to select the Extended Mode Register vs. the ...
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Commands Table 8 and Table 9 provide a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables, Table 11 on page 50, and Table 12 on page 52, appear following ...
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... WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the cor- responding data will be written to memory ...
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Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as ...
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SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. ...
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Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and ...
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Figure 11: Example: Meeting T0 T1 CK# CK COMMAND ACT NOP A0-A11 Row BA0, BA1 Bank x READs READ bursts are initiated with a READ command, as shown in Figure 12 on page 27. The starting column and bank addresses ...
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Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 17 on page 32. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued ...
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Figure 13: READ Burst T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ ...
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Figure 14: Consecutive READ Bursts T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n ...
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Figure 15: Nonconsecutive READ Bursts T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n ...
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Figure 16: Random READ Accesses T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n ...
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Figure 17: Terminating a READ Burst T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n ...
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Figure 18: READ to WRITE T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS CK# CK COMMAND READ Bank a, ADDRESS Col n DQS CK# CK COMMAND READ Bank a, ADDRESS Col n ...
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Figure 19: READ to PRECHARGE T0 CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND 6 READ Bank a, ADDRESS Col n DQS COMMAND READ Bank a, ADDRESS ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 20. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...
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Figure 20: WRITE Command x4: A0–A9, A11 x16: A9, A11 DON’T CARE Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, on page 41. Data for any ...
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Figure 21: WRITE Burst COMMAND ADDRESS t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following ...
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Figure 22: Consecutive WRITE to WRITE T0 CK# CK COMMAND WRITE Bank, ADDRESS Col b t DQSS (NOM) DQS DQ DM Notes etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied ...
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Figure 23: Nonconsecutive WRITE to WRITE T0 CK# CK COMMAND WRITE Bank, ADDRESS Col b t DQSS (NOM) DQS DQ DM Notes etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied ...
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Figure 24: Random WRITE Cycles T0 CK# CK COMMAND WRITE Bank, ADDRESS Col b t DQSS (NOM) DQS DQ DM Notes etc. = data-in for column b, etc. 2. b', etc. = the next data-in following DI ...
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Figure 25: WRITE to READ - Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 26: WRITE to READ - Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 27: WRITE to READ - Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS ...
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Figure 28: WRITE to PRECHARGE - Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 29: WRITE to Precharge – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 30: WRITE to PRECHARGE Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS ...
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PRECHARGE The PRECHARGE command, as shown in Figure 31, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subse- quent row access some specified ...
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CK, CK#, and CKE. For maxi- mum power savings, the DLL is frozen during precharge power-down mode. Exiting power-down requires the device the same voltage and frequency as when ...
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Table 10: Truth Table – CKE Notes: 1-6 CKE CKE Current State n Power-Down Self Refresh L H Power-Down Self Refresh H L All Banks Idle Bank(s) Active All Banks Idle H H Notes: 1. CKE clock ...
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Table 11: Truth Table – Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) Current State CS# RAS# CAS Any Idle ...
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Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when t t MRD has been met. Once • Precharging All: Starts with registration of a PRECHARGE ALL command and ends when is met, all ...
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Table 12: Truth Table – Current State Bank n - Command to Bank m (Notes: 1-6; notes appear below and on next page) Current State CS# RAS# Any Idle L L Row Activating, L ...
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This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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Table 15: DC Electrical Characteristics and Operating Conditions (-5B DDR400) 0°C ≤ T ≤ +70° Parameter/Condition Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) ...
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Table 16: AC Input Operating Conditions 0°C ≤ T ≤ +70° Notes appear on page 69-74 Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage Figure 33: Input Voltage Waveform Transmitter 09005aef8074a655 ...
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Table 17: Clock Input Operating Conditions 0°C ≤ T ≤ +70° Notes: 1–5, 15, 16, 5; notes appear on page 69-74 Parameter/Condition Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock ...
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Table 18: Capacitance (x4, x8 TSOP) Note: 13; notes appear on page 69-74 Parameter Delta Input/Output Capacitance: DQ0-DQ3 (x4), DQ0-DQ7 (x8) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command ...
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Table 21: I Specifications and Conditions (x4, x8; -5B) DD 0°C ≤ T ≤ +70° Notes: 1–5, 10, 12, 14, 14; notes appear on page 69-74; See also Table 26, Idd Test Cycle Times, on page 64 ...
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Table 22: I Specifications and Conditions (x4, x8; -6/-6T/-75E) DD 0°C ≤ T ≤ +70° Notes: 1–5, 10, 12, 14, 14; notes appear on page 69-74; See also Table 26, Idd Test Cycle Times, on page 64 ...
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Table 23: I Specifications and Conditions (x4, x8; -75Z/-75) DD 0°C ≤ T ≤ +70° Notes: 1–5, 10, 12, 14, 14; notes appear on page 69-74; See also Table 26, Idd Test Cycle Times, on page 64 ...
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Table 24: I Specifications and Conditions (x16; -6/-6T/-75E) DD 0°C ≤ T ≤ +70° Notes: 1–5, 10, 12, 14, 14; notes appear on page 69-74; See also Table 26, Idd Test Cycle Times, on page 64 Parameter/Condition ...
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Table 25: I Specifications and Conditions (x16; -75Z/-75) DD 0°C ≤ T ≤ +70° Notes: 1–5, 10, 12, 14, 14; notes appear on page 69-74; See also Table 26, Idd Test Cycle Times, on page 64 Parameter/Condition ...
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Table 26: I Test Cycle Times DD Values reflect number of clock cycles for each test. Speed Clock Cycle I Test Grade Time -75/75Z 7.5ns DD -75E 7.5ns -6/-6T 6ns -5B 5ns I 1 -75 7.5ns DD ...
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Table 27: Electrical Characteristics and Recommended AC Operating Conditions (-5B) Notes: 1–5, 14–17, 8; notes appear on page 69-74; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 28: Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E) Notes: 1–5, 14–17, 8; notes appear on page 69-74; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 29: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75) Notes: 1–5, 14–17, 8; notes appear on page 69-74; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 30: Input Slew Rate Derating Values for Addresses and Commands 0°C ≤ T ≤ +70° Speed Slew Rate 0.5 V/ns ≤ Slew Rate < 1.0 V/ns -75/-75Z/-75E 0.4 V/ns ≤ Slew Rate < 0.5 V/ns -75/-75Z/-75E ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I Output (V ...
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The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK REF 16. Inputs are not recognized as valid until ...
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Figure 35: Derating Data Valid Window ( 3.8 3.750 3.700 3.6 3.650 3.400 3.350 3.4 3.2 t —— - 10ns 3.0 t —— 10ns t —— - 7.5ns t —— ...
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The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 36. c. The full variation in driver pull-up ...
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The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and tem- perature. f. The ...
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During initialization, V Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the input pin. 13. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future ...
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Output Drive Characteristics and Timing Table 32: Normal Output Drive Characteristics Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 ...
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Table 33: Reduced Output Drive Characteristics Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.9 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 ...
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Figure 40: x4, x8 Data Output Timing – DQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ ...
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Figure 41: x16 Data Output Timing – CK# CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ0 - DQ7 and ...
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Figure 42: Data Output Timing – CK (MIN) 2 DQS, or LDQS/UDQS DQ (Last data valid) DQ (First data valid) 3 All DQ values, collectively t Notes: 1. DQSCK is the DQS output window relative ...
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Figure 43: Data Input Timing CK# CK DQS Notes: 1. DSH (MIN) generally occurs during t 2. DSS (MIN) generally occurs during 3. WRITE command issued at T0. 4. For x16, LDQS controls the lower byte and ...
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Initialization To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power Apply V 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at ...
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Figure 44: Initialization Flow Diagram Step 09005aef8074a655 128MBDDRx4x8x16_2.fm - Rev and V Q Ramp DD ...
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Timing Diagrams Figure 45: Initialize and Load Mode Registers ( ( ) ) VTD ( ( ) REF ) ) CK# ( ...
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Figure 46: Power-Down Mode T0 CK CKE VALID 2 COMMAND ADDR VALID DQS DQ DM Notes: 1. Once initialized, including during self refresh mode, V specified range. ...
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Figure 47: Auto Refresh Mode CKE NOP 2 COMMAND PRE A0-A9, 1 A11 ALL BANKS 1 A10 ONE BANK Bank(s) 4 ...
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Figure 48: Self Refresh Mode CK CKE COMMAND NOP AR ADDR DQS Enter Self Refresh ...
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Figure 49: Bank Read - Without Auto Precharge CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 x8: A11 ...
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Figure 50: Bank Read - With Auto Precharge CKE NOP 5 COMMAND ACT t IS x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 RA x8: A11 x16: ...
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Figure 51: Bank Write - Without Auto Precharge CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 x8: ...
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Figure 52: Bank Write - With Auto Precharge CKE NOP 5 COMMAND ACT x4: A0-A9, A11 RA x8: A0-A9 x16: A0-A8 x8: A11 ...
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Figure 53: Write - DM Operation CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 x8: A11 RA ...
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Package Dimensions Figure 54: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP PIN #1 ID Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold ...
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Figure 55: 60-Ball FBGA (16 x 9mm) 0.850 ±0.075 SEATING PLANE C 0.10 C 60X Ø .45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40mm. BALL A9 11.00 5.50 ±0.05 3.20 ±0.05 4.50 ±0.05 ...