MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 74

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
12. During initialization, V
13. The current Micron part operates below the slowest JEDEC operating frequency of 83
14. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic
15. Random addressing, 50 percent of data changing at every transfer.
16. Random addressing, 100 percent of data changing at every transfer.
17. CKE must be active (HIGH) during the entire time a refresh command is executed.
18. I
19. Whenever the operating frequency is altered, not including jitter, the DLL is required
20. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz.
21. The -6/-6T speed grades will operate with
Alternatively, V
provided a minimum of 42Ω of series resistance is used between the V
the input pin.
MHz. As such, future die may not reflect this option.
low.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until
I
remain stable. Although I
to be reset followed by 200 clock cycles before any READ command.
Any noise above 20 MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V±100mV.
120,000ns at any slower frequency.
DD
DD
2N specifies the DQ, DQS and DM to be driven to a valid high or low logic level.
2Q is similar to I
TT
may be 1.35V maximum during power up, even if V
DD
DD
2F except I
DD
Q, V
74
2F, I
TT
DD
, and V
2N, and I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC has been satisfied.
2Q specifies the address and control inputs to
REF
must be equal to or less than V
DD
128Mb: x4, x8, x16 DDR SDRAM
2Q are similar, I
t
RAS(min) = 40ns and
©2000 Micron Technology, Inc. All rights reserved.
DD
2F is “worst case.”
DD
t
/V
TT
RAS(max) =
DD
supply and
DD
Q are 0V,
Notes
+ 0.3V.