MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 52

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Table 12:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto-
Precharge
Disabled)
Write
(Auto-
Precharge
Disabled)
Read
(With Auto-
Precharge)
Write
(With Auto-
Precharge)
Current State
• Idle: The bank has been precharged, and
• Row Active: A row in the bank has been activated, and
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
• Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
• Read with Auto Precharge Enabled: See following text – 3a
• Write with Auto Precharge Enabled: See following text – 3a
register accesses are in progress.
minated.
minated
Truth Table – Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes: 1. This table applies when CKE
a. The read with auto precharge enabled or write with auto precharge enabled states can each be
broken into two parts: the access period and the precharge period. For read with auto precharge,
the precharge period is defined as if the same burst was executed with auto precharge disabled
and then followed with the earliest possible PRECHARGE command that still accesses all of the
data in the burst. For write with auto precharge, the precharge period begins when
with
of the command and ends where the precharge period (or
RAS#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
2. This table describes alternate bank operation, except where noted (i.e., the current state is
3. Current state definitions:
t
WR measured as if auto precharge was disabled. The access period starts with registration
t
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
XSNR has been met (if the previous state was self refresh).
CAS#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
WE#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
t
RP has been met.
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
52
n-1
t
was HIGH and CKE
RCD has been met. No data bursts/accesses and no
Command/Action
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
n
is HIGH (see Truth Table 2) and after
t
RP) begins.
©2000 Micron Technology, Inc. All rights reserved.
Operations
t
WR ends,
7, 9, 3a
Notes
7, 3a
7, 3a
7, 3a
7, 9
7, 8
7
7
7
7