HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 45

IC DDR2 SDRAM 1GBIT 84TFBGA

HYB18T1G160BF-5

Manufacturer Part Number
HYB18T1G160BF-5
Description
IC DDR2 SDRAM 1GBIT 84TFBGA
Manufacturer
Qimonda
Datasheet

Specifications of HYB18T1G160BF-5

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (64M x 16)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 95°C
Package / Case
84-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
675-1018-2
7
This chapter contains speed grade definition, AC timing parameter and ODT tables.
7.1
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications (
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined .
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
Timing Characteristics
Speed Grade Definitions
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
V
REF
V
stabilizes. During the period before
TT
Symbol
t
t
t
t
t
t
t
t
.
CK
CK
CK
CK
RAS
RC
RCD
RP
DDR2–800D
–2.5F
5–5–5
Min.
5
3.75
2.5
2.5
45
57.5
12.5
12.5
45
Speed Grade Definition Speed Bins for DDR2–800
8
Max.
8
8
8
70000
V
REF
stabilizes, CKE = 0.2 x
1-Gbit Double-Data-Rate-Two SDRAM
DDR2–800E
–2.5
6–6–6
Min.
5
3.75
3
2.5
45
60
15
15
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
t
CK
8
8
8
Max.
8
70000
= 5ns with
V
DDQ
Internet Data Sheet
t
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
RAS
CK
is recognized as low.
TABLE 49
= 40ns).
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.

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