HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 56

• Manufacturer Part Number: HYB18T1G160BF-5
• Description: IC DDR2 SDRAM 1GBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T1G160BF-5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1018-2

Rev. 1.3, 2007-07
03062006-ZNH8-HURV
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data
strobe)
DQS falling edge hold time from CK (write
cycle)
DQS falling edge to CK setup time (write cycle)
Four Activate Window period
Four Activate Window period
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
FAW
FAW
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MOD
MRD
OIT
(base)
(base)
(base)
(base)
(base)
(base)
56
DDR2–533
–500
2
0.45
3
0.45
WR +
t
225
–25
0.35
–450
0.35
—
– 0.25
100
–25
0.2
0.2
37.5
50
MIN. (
—
375
0.6
250
2 ×
t
0
2
0
Min.
IS
AC.MIN
+
t
t
AC.MIN
CK
t
t
CL,
RP
+
t
t
CH
IH
)
1-Gbit Double-Data-Rate-Two SDRAM
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
Max.
+500
—
0.55
—
0.55
—
––
––
—
—
+450
—
300
+ 0.25
—
—
—
—
—
—
t
—
—
—
t
t
12
—
12
AC.MAX
AC.MAX
AC.MAX
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
ns
ns
ps
ps
t
ps
ps
ps
ns
t
ns
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 55
Note
6)
7)17)
8)
9)
10)
10)
10)
10)
12)
11)
12)
10)
10)
13)
13)
1)2)3)4)5)