HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 64

• Manufacturer Part Number: HYB18T1G160BF-5
• Description: IC DDR2 SDRAM 1GBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T1G160BF-5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1018-2

7.4
This chapter describes the ODT AC electrical characteristics.
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
1) New units, “t
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
Symbol
t
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
the ODT resistance is fully on. Both are measured from
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if
Both are measured from
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
under operation. Unit “
DDR2-533, “
be registered at
ODT resistance is fully on. Both are measured from
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
CK.AVG
t
CK
” is used for both concepts. Example:
T
m
” and “
+ 2, even if (
ODT AC Electrical Characteristics
n
CK
t
n
t
AOFD
AOFD
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
CK
”, are introduced in DDR2-667 and DDR2-800. Unit “
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400
ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800
. Both are measured from
, which is interpreted differently per speed bin. For DDR2-667/800, if
T
m
+ 2 -
T
m
) is 2 x
t
t
CK.AVG
AOND
t
XP
t
, which is interpreted differently per speed bin. For DDR2-667/800,
t
= 2 [
AOND
AOFD
+
t
ERR.2PER(Min)
n
, which is interpreted differently per speed bin. For DDR2-400/533,
, which is interpreted differently per speed bin. For DDR2-400/533,
CK
Values
Min.
2
t
t
2.5
t
t
3
8
Values
Min.
2
t
t
2.5
t
t
3
8
] means; if Power Down exit is registered at
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
64
+ 2 ns
+ 2 ns
+ 2 ns
+ 2 ns
.
t
CK
= 5 ns.
t
CK
= 5 ns.
t
CK.AVG
Max.
2
t
2
t
2.5
—
Max.
2
t
2
t
2.5
—
2.5
—
2.5
—
AC.MAX
AC.MAX
AC.MAX
AC.MAX
t
t
CK +
CK +
t
t
” represents the actual
1-Gbit Double-Data-Rate-Two SDRAM
CK +
CK +
t
t
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
+ 1 ns
AC.MAX
+ 0.6 ns
+ 0.7 ns
AC.MAX
+ 0.6 ns
t
t
AC.MAX
AC.MAX
+ 1 ns
+ 1 ns
t
CK(avg)
+ 1 ns
+ 1 ns
= 3 ns is assumed,
T
m
, an Active command may
t
CK.AVG
Internet Data Sheet
Unit
t
ns
ns
t
ns
ns
t
t
Unit
n
ns
ns
n
ns
ns
n
n
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 60
TABLE 61
of the input clock
t
AOND
Note
Note
1)
2)
1)
1)2)
1)
1)
1)3)
1)
1)
1)
t
AOFD
is 2 clock
t
t
AOND
AOFD
is 1.5
is
is