AT25DF321A-SH-T Atmel, AT25DF321A-SH-T Datasheet
AT25DF321A-SH-T
Specifications of AT25DF321A-SH-T
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AT25DF321A-SH-T Summary of contents
Page 1
... Data Retention: 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (208-mil wide) – 8-pad Ultra Thin DFN ( 0.6mm) 32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory Atmel AT25DF321A 3686D–DFLASH–12/09 ...
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... EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF321A have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently ...
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... GROUND: The ground reference for the power supply. GND should be connected to the system GND ground. 3686D–DFLASH–12/09 for more details on protection features and the pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. Atmel AT25DF321A Asserted State Low - - - Low ...
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... SO (SOI) SCK 6 SI (SIO) 5 CONTROL AND PROTECTION LOGIC Y-DECODER X-DECODER ® 8-UDFN (Top View) CS VCC 1 8 HOLD SCK 3 6 GND SI (SIO I/O BUFFERS AND LATCHES DATA BUFFER Y-GATING FLASH MEMORY ARRAY AT25DF321A can be erased in four levels of granularity SRAM 3686D–DFLASH–12/09 ...
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... Figure 4-1. Memory Architecture Diagram 3686D–DFLASH–12/09 Atmel AT25DF321A 5 ...
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... The SPI protocol defines a total of four modes of operation (mode with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF321A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data) ...
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... Up to 100MHz 01h 0000 0001 Up to 100MHz 31h 0011 0001 Up to 100MHz F0h 1111 0000 Up to 100MHz 9Fh 1001 1111 Up to 85MHz B9h 1011 1001 Up to 100MHz ABh 1010 1011 Up to 100MHz Atmel AT25DF321A Address Dummy Data Bytes Bytes Bytes ...
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... A MSB MSB HIGH-IMPEDANCE SO Atmel AT25DF321A 8 , and the 03h opcode can be used for lower frequency read operations up CLK . The 1Bh opcode allows the highest read performance possible and can be used at any RDLF ; however, use of the 1Bh opcode at clock frequencies above f MAX ™ ...
Page 9
... Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. 3686D–DFLASH–12/ ADDRESS BITS A23- MSB MSB ADDRESS BITS A23- MSB D MSB Atmel AT25DF321A DON'T CARE DATA BYTE MSB DATA BYTE MSB 46 ...
Page 10
... CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected or locked down. Atmel AT25DF321A ...
Page 11
... Program command, all data clocked into the device is stored in an internal buffer. 3686D–DFLASH–12/ ADDRESS BITS A23- MSB ADDRESS BITS A23- MSB MSB ) to set the Write Enable Latch (WEL) bit of the Status “Write Enable” on page 18 Atmel AT25DF321A or t time to determine if the DATA MSB DATA IN BYTE 1 DATA IN BYTE MSB ...
Page 12
... If a programming error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-3. Dual-Input Byte Program SCK OPCODE MSB HIGH-IMPEDANCE SOI Atmel AT25DF321A only programming a single byte then the Byte/Page Program command will not be executed, and the ADDRESS BITS A23-A0 0 ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. 3686D–DFLASH–12/ ADDRESS BITS A23- MSB . BLKE Atmel AT25DF321A INPUT INPUT INPUT DATA BYTE 1 DATA BYTE 2 DATA BYTE ...
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... Register will be reset back to the logical “0” state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. Chip Erase SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF321A ADDRESS BITS A23- ...
Page 15
... Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE (Sector Lockdown Enabled) bits, will not be affected. 3686D–DFLASH–12/09 outlines the operations that are allowed and not allowed during Table 8 performed while a sector is erase suspended, the suspend operation will Atmel AT25DF321A 15 ...
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... Read OTP Security Register Status Register Commands Read Status Register Write Status Register (All Opcodes) Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down Atmel AT25DF321A 16 Operation During Operation During Program Suspend Erase Suspend Allowed Allowed Not Allowed ...
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... RDY/BSY bit or the appropriate bit in the Status Register to determine if the previously suspended program or erase operation has resumed. Figure 8-8. Program/Erase Resume SCK OPCODE MSB HIGH-IMPEDANCE SO 3686D–DFLASH–12/ time before issuing the Program/Erase Suspend command must check the RES Atmel AT25DF321A . RES 17 ...
Page 18
... When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Atmel AT25DF321A 18 4 ...
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... Status Register description for more details). If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. 3686D–DFLASH–12/ Atmel AT25DF321A 19 ...
Page 20
... Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF321A ADDRESS BITS A23- ...
Page 21
... Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. 3686D–DFLASH–12/09 “Write Status Register Byte 1” on page 34 details the conditions necessary for a Global Protect or Global Unprotect to be Table 9-2 Atmel AT25DF321A for command 21 ...
Page 22
... SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-locking or hardware-locking is desired along with the Global Protect. Atmel AT25DF321A 22 Bit Protection Operation Global Unprotect – ...
Page 23
... HIGH-IMPEDANCE SO 3686D–DFLASH–12/09 and Table 11-1 on page 30 , the first byte of data output will not be valid. Therefore, if operating at clock frequencies CLK ADDRESS BITS A23- MSB Atmel AT25DF321A for details on the Status Register format and what DATA BYTE MSB MSB “Read Status 23 ...
Page 24
... Hardware 0 1 Locked 1 0 Software 1 1 Locked Atmel AT25DF321A 24 Sector Protection Register ( SPRL Change Allowed Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector Can be modified from commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands Locked will be ignored ...
Page 25
... CS pin has been deasserted. 3686D–DFLASH–12/ issue the Sector Lockdown command, the CS pin must first be asserted . In addition, the WEL bit in the Status Register will be reset back to the LOCK Atmel AT25DF321A “Freeze Sector Lockdown State” 25 ...
Page 26
... When the device aborts the Freeze Sector Lockdown State operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. Figure 10-2. Freeze Sector Lockdown State SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF321A ADDRESS BITS A23-A0 CONFIRMATION BYTE ...
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... Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. 3686D–DFLASH–12/09 , the first byte of data output will not be valid. Therefore, if operating at clock frequencies CLK ADDRESS BITS A23- MSB MSB Atmel AT25DF321A DON'T CARE DATA BYTE ...
Page 28
... For faster throughput recommended that the Status Register be polled rather than waiting the t time to determine if the data bytes have finished programming. At some point before the OTP Security Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state. Atmel AT25DF321A 28 Security Register ...
Page 29
... HIGH-IMPEDANCE SO 3686D–DFLASH–12/ ADDRESS BITS A23- MSB MSB . To read the OTP Security Register, the CS pin must first be asserted and the opcode of MAX ADDRESS BITS A23- MSB MSB Atmel AT25DF321A DATA IN BYTE 1 DATA IN BYTE MSB DON'T CARE DATA BYTE MSB MSB 29 ...
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... Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command 2. R/W = Readable and writeable R = Readable only Atmel AT25DF321A 30 , the first two bytes of data output from the Status Register will not be valid. Therefore, if CLK , at least four bytes of data must be clocked out from the device in order to read ...
Page 31
... The EPE bit will be updated after every erase and program operation. 3686D–DFLASH–12/09 (2) Name Type R/W R Atmel AT25DF321A Description 0 Reserved for future use 0 Reserved for future use 0 Reserved for future use 0 Reset command is disabled (default) 1 Reset command is enabled Sector Lockdown and Freeze Sector Lockdown State ...
Page 32
... The RSTE bit will retain its state as long as power is applied to the device. Once set to the logical “1” state, the RSTE bit will remain in that state until it is modified using the Write Status Register Byte 2 command or until the device has been power cycled. The Reset command itself will not change the state of the RSTE bit. Atmel AT25DF321A 32 3686D–DFLASH–12/09 ...
Page 33
... RDY/BSY bit changes from a logical “1” logical “0”. Figure 11-1. Read Status Register SCK OPCODE MSB HIGH-IMPEDANCE SO 3686D–DFLASH–12/ STATUS REGISTER BYTE MSB MSB Atmel AT25DF321A STATUS REGISTER STATUS REGISTER BYTE 2 BYTE MSB ...
Page 34
... Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 11-3. Write Status Register Byte 1 Format Bit 7 Bit 6 SPRL X Figure 11-2. Write Status Register Byte SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF321A 34 for more details. Bit 5 Bit 4 Bit 3 Global Protect/Unprotect STATUS REGISTER IN BYTE ...
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... Write Status Register Byte 2 Format Bit 7 Bit Figure 11-3. Write Status Register Byte SCK OPCODE MSB HIGH-IMPEDANCE SO 3686D–DFLASH–12/09 Bit 5 Bit 4 Bit 3 X RSTE SLE STATUS REGISTER IN BYTE MSB Atmel AT25DF321A ). Any additional data bytes that are sent to the Table 11-4 Bit 2 Bit 1 Bit ...
Page 36
... The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. Figure 12-1. Reset SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF321A CONFIRMATION BYTE ...
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... Density Code Product Version Code Atmel AT25DF321A . Since not all Flash devices CLK Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25DF/26DFxxx series) 47h Density Code: 00111 (32-Mbit) 1 Sub Code: 000 (Standard series) 01h ...
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... The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Atmel AT25DF321A 38 7 ...
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... Deep Power-Down mode. Figure 12-4. Resume from Deep Power-Down SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Deep Power-Down Mode Current 3686D–DFLASH–12/09 t EDPD Deep Power-Down Mode Current t RDPD Standby Mode Current Atmel AT25DF321A and return to the standby mode. After the RDPD 39 ...
Page 40
... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 12-5. Hold Mode CS SCK HOLD Atmel AT25DF321A 40 Hold Hold Hold 3686D–DFLASH–12/09 ...
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... SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DF321A a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... Max 33MHz 0mA; OUT Max 20MHz 0mA; OUT Max Max Max CMOS levels CMOS levels OUT 0 1.6mA Min -100 µ Min Atmel AT25DF321A -40°C to 85°C 2.7V to 3.6V Min Typ Max 0 0.4 -0.2V 3686D–DFLASH–12/09 Units µA µ µA µ ...
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... Sector Protect Time (from Chip Select High) SECP (1) t Sector Unprotect Time (from Chip Select High) SECUP (1) t Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High) LOCK 3686D–DFLASH–12/09 Atmel AT25DF321A Min Max Units 100 MHz 85 MHz 50 MHz 85 ...
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... VCSL CC t Power-up Device Delay Before Program or Erase Allowed PUW V Power-on Reset Voltage POR 14.8 Input Test Waveforms and Measurement Levels 0. DRIVING LEVELS 0. < (10 Atmel AT25DF321A 44 4-Kbytes 32-Kbytes 64-Kbytes Program Erase Program Erase MEASUREMENT CC LEVEL Min Max Units 1 µs 30 µs 30 µ ...
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... MHz) or 30pF 15. AC Waveforms Figure 15-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 15-2. Serial Output Timing CS SCK 3686D–DFLASH–12/09 t CSLH t t CLKH CLKL t DH LSB t CLKH Atmel AT25DF321A t CSH t CSHH t CSHS MSB t t CLKL DIS 45 ...
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... BYTE 1 OPCODE HIGH-IMPEDANCE SO Figure 15-4. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI t HLQZ SO Atmel AT25DF321A 46 t WPH LSB OF WRITE STATUS REGISTER DATA BYTE t t HHH HLS t HLH t HLS t HLH ...
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... Package AT25DF321A-MH-Y 8MA1 AT25DF321A-MH-T AT25DF321A-SH-B 8S2 AT25DF321A-SH-T Notes: 1. The shipping carrier option code is not marked on the devices 8MA1 8-pad ( 0.6mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) 8S2 8-lead, 0.208” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 3686D– ...
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... UDFN E Pin TOP VIEW Pin #1 Notch (0.20 R) (Option BOTTOM VIEW L Package Drawing Contact: packagedrawings@atmel.com Atmel AT25DF321A 48 SIDE VIEW A1 A 0.45 Option A 1 Pin #1 Chamfer (C 0.35) SYMBOL TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead ...
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... TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) Atmel AT25DF321A θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 ...
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... Increased typical I Changed Chip Erase time – Decreased typical value from 32 sec to 25 sec and max value from 56 sec to 40 sec – Remove Preliminary Atmel AT25DF321A 50 Table 6-1 value for 100MHz from 12mA to 17mA and max value from 19mA to 20mA ...
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