AT25DF321A-SH-T Atmel, AT25DF321A-SH-T Datasheet - Page 18

• Manufacturer Part Number: AT25DF321A-SH-T
• Description: IC FLASH 32MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF321A-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (16384 pages x 256 Bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 32Mb
• Access Time (max): 5ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
9.1
9.2
18
Protection Commands and Features
Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state.
The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze
Sector Lockdown State, Program OTP Security Register, or Write Status Register command can be executed. This makes
the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or
erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then
the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must
be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary
(multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change.
Figure 9-1.
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical "0"
state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze
Sector Lockdown State, Program OTP Security Register, and Write Status Register commands will not be executed. Other
conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register
description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode must
be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary
(multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change.
SCK
Atmel AT25DF321A
SO
CS
SI
Write Enable
MSB
HIGH-IMPEDANCE
0
0
0
1
0
2
OPCODE
0
3
0
4
1
5
1
6
0
7
3686D–DFLASH–12/09