AT25DF321A-SH-T Atmel, AT25DF321A-SH-T Datasheet - Page 35

• Manufacturer Part Number: AT25DF321A-SH-T
• Description: IC FLASH 32MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF321A-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (16384 pages x 256 Bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 32Mb
• Access Time (max): 5ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Atmel AT25DF321A
11.3
Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using the Write
Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register during normal
device operation, and the SLE bit can only be modified if the sector lockdown state has not been frozen. Before the Write
Status Register Byte 2 command can be issued, the Write Enable command must have been previously issued to set the
WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h must be
clocked into the device followed by one byte of data. The one byte of data consists of three don’t care bits, the RSTE bit
value, the SLE bit value, and three additional don’t care bits (see
). Any additional data bytes that are sent to the
Table 11-4
device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status Register will be modified, and
the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit will only be modified if the Freeze Sector
Lockdown State command has not been previously issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of
the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the logical “0” state.
Table 11-4.
Write Status Register Byte 2 Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
RSTE
SLE
X
X
X
Figure 11-3. Write Status Register Byte 2
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14 15
SCK
STATUS REGISTER IN
OPCODE
BYTE 2
SI
0
0
1
1
0
0
0
1
X
X
X
D
D
X
X
X
MSB
MSB
HIGH-IMPEDANCE
SO
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3686D–DFLASH–12/09