MA240029 Microchip Technology, MA240029 Datasheet - Page 21

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

TABLE 1-4:
 2010-2011 Microchip Technology Inc.
PGEC1
PGED1
PGEC2
PGED2
PGEC3
PGED3
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMA22
PMACK1
PMACK2
PMBE0
PMBE1
PMCS1
PMCS2
Legend:
Function
Pin
TTL = TTL input buffer
ANA = Analog level input/output
64-Pin
TQFP
15
16
17
18
12
28
27
24
23
45
44
11
30
29
16
22
32
31
—
—
—
—
—
—
—
50
43
51
—
—
—
8
6
5
4
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
80-Pin
TQFP
19
34
33
30
29
57
56
20
21
22
15
16
36
35
10
24
23
40
39
—
—
—
14
—
—
52
62
55
63
53
13
—
8
7
6
100-Pin
TQFP
24
42
41
35
34
71
70
95
92
40
60
25
26
27
20
21
44
43
14
12
11
10
29
28
50
49
19
59
66
77
69
78
67
18
9
121-Pin
ST = Schmitt Trigger input buffer
I
BGA
2
G10
C11
D11
G11
A10
E10
L11
L10
E11
C4
G2
G1
K1
K2
H1
H2
K7
F3
F2
F4
E3
K3
L7
L5
B5
K6
B9
E8
E1
C™ = I
L1
J3
L8
L2
J7
J5
PIC24FJ128GA310 FAMILY
2
C/SMBus input buffer
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
ST/TTL Parallel Master Port Acknowledge Input 1.
ST/TTL Parallel Master Port Acknowledge Input 2.
ST/TTL Parallel Master Port Chip Select 1 Strobe.
Buffer
Input
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
In-Circuit Debugger/Emulator/ICSP™ Programming
Clock.
In-Circuit Debugger/Emulator/ICSP Programming
Data.
In-Circuit Debugger/Emulator/ICSP Programming
Clock.
In-Circuit Debugger/Emulator/ICSP Programming
Data.
In-Circuit Debugger/Emulator/ICSP Programming
Clock.
In-Circuit Debugger/Emulator/ICSP Programming
Data.
Parallel Master Port Address Bit 0 Input (Buffered
Slave modes) and Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered
Slave modes) and Output (Master modes).
Parallel Master Port Address (bits<22:2>).
Parallel Master Port Byte Enable 0 Strobe.
Parallel Master Port Byte Enable 1 Strobe.
Parallel Master Port Chip Select 2 Strobe.
Description
DS39996F-page 21