MA240029 Microchip Technology, MA240029 Datasheet - Page 238

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
REGISTER 17-2:
DS39996F-page 238
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
ACKSTAT
R/C-0, HS
R-0, HSC
IWCOL
ACKSTAT: Acknowledge Status bit
1 = NACK was detected last
0 = ACK was detected last
Hardware is set or cleared at the end of Acknowledge.
TRSTAT: Transmit Status bit
(when operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge.
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at the detection of a bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when the address matches the general call address; hardware is clear at Stop detection.
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I
0 = No collision
Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D/A: Data/Address bit (when operating as I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at the device address match. Hardware is set after a transmission finishes or by
reception of a slave byte.
R/C-0, HS
R-0, HSC
TRSTAT
I2COV
I2CxSTAT: I2Cx STATUS REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R-0, HSC
D/A
U-0
—
2
C™ master; applicable to master transmit operation.)
R/C-0, HSC
U-0
—
P
nd
byte of the matched 10-bit address; hardware is clear at Stop detection.
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-0, HSC
2
C slave)
U-0
—
S
R/C-0, HS
R-0, HSC
BCL
R/W
2
 2010-2011 Microchip Technology Inc.
C module is busy
x = Bit is unknown
R-0, HSC
R-0, HSC
GCSTAT
RBF
R-0, HSC
R-0, HSC
ADD10
TBF
bit 8
bit 0