MA240029 Microchip Technology, MA240029 Datasheet - Page 344

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
29.3
For PIC24FJ128GA310 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0> Con-
figuration bits (CW1<3:0>), which allows the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed.
(RCON<3:2>) bits will need to be cleared in software
after the device wakes up.
FIGURE 29-2:
DS39996F-page 344
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Sleep or Idle Mode
New Clock Source
All Device Resets
FWDTEN<1:0>
CLRWDT Instr.
PWRSAV Instr.
Exit Sleep or
Transition to
LPRC Input
Watchdog Timer (WDT)
Idle Mode
SWDTEN
The
corresponding
WDT BLOCK DIAGRAM
WDT
31 kHz
) of 1 ms in 5-bit mode or
SLEEP
(5-bit/7-bit)
Prescaler
FWPSA
1 ms/4 ms
or
LPRC Control
IDLE
Counter
WDT
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
29.3.1
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<7>) to ‘0’.
29.3.2
The WDT is enabled or disabled by the FWDTEN<1:0>
Configuration bits. When the Configuration bits,
FWDTEN<1:0> = 11, the WDT is always enabled.
The WDT can be optionally controlled in software when
the Configuration bits, FWDTEN<1:0> = 10. When
FWDTEN<1:0> = 00, the Watchdog Timer is always
disabled. The WDT is enabled in software by setting
the SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
Note:
1:1 to 1:32.768
WDTPS<3:0>
Postscaler
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WINDOWED OPERATION
CONTROL REGISTER
 2010-2011 Microchip Technology Inc.
Wake from Sleep
WDT Overflow
Reset