MA240029 Microchip Technology, MA240029 Datasheet - Page 338

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
REGISTER 29-3:
DS39996F-page 338
bit 23
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 23-16
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9
bit 8
bit 7
Note 1:
VBTBOR
WPEND
R/PO-1
R/PO-1
U-1
—
2:
3:
Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word page, the
Configuration Word page is protected.
Ensure that the SCLKI pin is made a digital input while using this configuration (see
For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be
maintained as ‘0’.
Unimplemented: Read as ‘1’
WPEND: Segment Write Protection End Page Select bit
1 = Protected code segment upper boundary is at the last page of program memory; the lower
0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper
WPCFG: Configuration Word Code Page Write Protection Select bit
1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected
0 = Last page and Flash Configuration Words are write-protected provided WPDIS = ‘0’
WPDIS: Segment Write Protection Disable bit
1 = Segmented code protection is disabled
0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and
BOREN: Brown-out Reset Enable bit
1 = BOR is enabled (all modes except Deep Sleep)
0 = BOR is disabled
WDTWIN<1:0>: Watchdog Timer Window Width Select bits
11 = 25%
10 = 37.5%
01 = 50%
00 = 75%
Reserved: Always maintain as ‘1’
SOSCSEL: SOSC Selection bit
1 = SOSC circuit is selected
0 = Digital (SCLKI) mode
VBTBOR: V
1 = V
0 = V
WPFP6
WPCFG
R/PO-1
R/PO-1
boundary is the code page specified by WPFP<6:0>
boundary is the code page specified by WPFP<6:0>
WPFPx Configuration bits
U-1
—
BAT
BAT
CW3: FLASH CONFIGURATION WORD 3
(3)
BOR is enabled
BOR is disabled
BAT
PO = Program Once bit
W = Writable bit
‘1’ = Bit is set
BOR Enable bit
WPFP5
R/PO-1
WPDIS
R/PO-1
U-1
—
(2)
BOREN
WPFP4
R/PO-1
R/PO-1
U-1
—
r = Reserved bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WDTWIN1
WPFP3
R/PO-1
R/PO-1
U-1
—
WDTWIN0
R/PO-1
WPFP2
R/PO-1
U-1
—
 2010-2011 Microchip Technology Inc.
x = Bit is unknown
WPFP1
R/PO-1
U-1
r-1
—
r
Table
11-1).
SOSCSEL
WPFP0
R/PO-1
R/PO-1
U-1
—
bit 16
bit 8
bit 0
(1)