MA240029 Microchip Technology, MA240029 Datasheet - Page 247

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

REGISTER 18-2:
 2010-2011 Microchip Technology Inc.
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
The value of the bit only affects the transmit properties of the module when the IrDA
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)”
The TRMT bit will be active only after two instruction, cycles once the UTXREG is loaded.
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0 = Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1  0 transition); will reset
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
the receiver buffer and the RSR to the empty state
receive buffer has one or more characters
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
PIC24FJ128GA310 FAMILY
for more information.
®
encoder is enabled
DS39996F-page 247