MA240029 Microchip Technology, MA240029 Datasheet - Page 89
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MA240029
Manufacturer Part Number
MA240029
Description
Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
Manufacturer
Microchip Technology
Datasheet
1.MA240029.pdf
(406 pages)
Specifications of MA240029
Rohs
yes
Product
Daughter Cards
Core
PIC
Description/function
Plug-in module
Interface Type
I2C, SPI
Tool Is For Evaluation Of
PIC24FJ128GA310
For Use With
Explorer 16 Development Board
Available stocks
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Part Number
Manufacturer
Quantity
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Part Number:
MA240029
Manufacturer:
MICROCHIP
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12 000
- Current page: 89 of 406
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7.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in
FIGURE 7-1:
2010-2011 Microchip Technology Inc.
Note:
RESETS
Figure
MCLR
Section 7. “Reset” (DS39712). The infor-
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
mation in this data sheet supersedes the
information in the FRM.
V
Enable Voltage Regulator
DD
Uninitialized W Register
Configuration Mismatch
7-1.
Illegal Opcode
Family
RESET SYSTEM BLOCK DIAGRAM
Trap Conflict
Sleep or Idle
Brown-out
V
RESET
Instruction
Module
Detect
DD
WDT
Reset
Rise
Reference
Glitch Filter
Manual”,
PIC24FJ128GA310 FAMILY
POR
BOR
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see
while an extreme power-saving feature is in use (such
as V
register
for the BOR and POR (RCON<1:0>) bits, which are
set. The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
Note:
Note:
BAT
Register
) will set one or more status bits in the RCON2
(Register
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON registers
should be cleared after they are read so
that the next RCON register values after a
device Reset will be meaningful.
7-1). In addition, Reset events occurring
7-2). A POR will clear all bits, except
DS39996F-page 89
SYSRST
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