M25P64-VMF6TP NUMONYX, M25P64-VMF6TP Datasheet - Page 27
![IC FLASH 64MBIT 50MHZ 16SOIC](/photos/7/28/72855/m25p64-vmf6tp_sml.jpg)
M25P64-VMF6TP
Manufacturer Part Number
M25P64-VMF6TP
Description
IC FLASH 64MBIT 50MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P64-VME6TG.pdf
(55 pages)
Specifications of M25P64-VMF6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8M x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P64-VMF6TP
M25P64-VMF6TPTR
M25P64-VMF6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P64-VMF6TP
Manufacturer:
Numonyx
Quantity:
1 000
Company:
Part Number:
M25P64-VMF6TP
Manufacturer:
MICRONEOL84
Quantity:
1 016
Part Number:
M25P64-VMF6TP
Manufacturer:
STM
Quantity:
20 000
Company:
Part Number:
M25P64-VMF6TP-6JBS
Manufacturer:
OKI
Quantity:
270
Company:
Part Number:
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Manufacturer:
STMicroelectronics
Quantity:
500
Company:
Part Number:
M25P64-VMF6TPBA
Manufacturer:
MICRON
Quantity:
1 001
6.4.4
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/V
(W/V
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
PP
) signal allow the device to be put in the Hardware Protected mode (when the Status
PP
sequence
0
High Impedance
) signal. The Status Register Write Disable (SRWD) bit and Write Protect
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
Table
4
PP
3
) is driven Low). In
2) becomes
2
1
0
7
AI02031E
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