M25P64-VMF6TP NUMONYX, M25P64-VMF6TP Datasheet - Page 29
![IC FLASH 64MBIT 50MHZ 16SOIC](/photos/7/28/72855/m25p64-vmf6tp_sml.jpg)
M25P64-VMF6TP
Manufacturer Part Number
M25P64-VMF6TP
Description
IC FLASH 64MBIT 50MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P64-VME6TG.pdf
(55 pages)
Specifications of M25P64-VMF6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8M x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P64-VMF6TP
M25P64-VMF6TPTR
M25P64-VMF6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P64-VMF6TP
Manufacturer:
Numonyx
Quantity:
1 000
Company:
Part Number:
M25P64-VMF6TP
Manufacturer:
MICRONEOL84
Quantity:
1 016
Part Number:
M25P64-VMF6TP
Manufacturer:
STM
Quantity:
20 000
Company:
Part Number:
M25P64-VMF6TP-6JBS
Manufacturer:
OKI
Quantity:
270
Company:
Part Number:
M25P64-VMF6TP-N
Manufacturer:
STMicroelectronics
Quantity:
500
Company:
Part Number:
M25P64-VMF6TPBA
Manufacturer:
MICRON
Quantity:
1 001
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/V
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/V
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect/ (W/V
If Write Protect/ (W/V
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write Status Register (WRSR) instruction sequence
If Write Protect (W/V
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/V
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/V
or by driving Write Protect (W/V
(SRWD) bit.
PP
) Low
S
C
D
Q
PP
) High.
PP
) is permanently tied High, the Hardware Protected Mode (HPM) can
PP
PP
0
) is driven High, it is possible to write to the Status Register
) is driven Low, it is not possible to write to the Status Register
1
High Impedance
2
Instruction
PP
3
) is driven High or Low.
PP
4
) Low after setting the Status Register Write Disable
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
AI02282D
PP
):
29/55