M25P64-VMF6TP NUMONYX, M25P64-VMF6TP Datasheet - Page 35
![IC FLASH 64MBIT 50MHZ 16SOIC](/photos/7/28/72855/m25p64-vmf6tp_sml.jpg)
M25P64-VMF6TP
Manufacturer Part Number
M25P64-VMF6TP
Description
IC FLASH 64MBIT 50MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P64-VME6TG.pdf
(55 pages)
Specifications of M25P64-VMF6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8M x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P64-VMF6TP
M25P64-VMF6TPTR
M25P64-VMF6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P64-VMF6TP
Manufacturer:
Numonyx
Quantity:
1 000
Company:
Part Number:
M25P64-VMF6TP
Manufacturer:
MICRONEOL84
Quantity:
1 016
Part Number:
M25P64-VMF6TP
Manufacturer:
STM
Quantity:
20 000
Company:
Part Number:
M25P64-VMF6TP-6JBS
Manufacturer:
OKI
Quantity:
270
Company:
Part Number:
M25P64-VMF6TP-N
Manufacturer:
STMicroelectronics
Quantity:
500
Company:
Part Number:
M25P64-VMF6TPBA
Manufacturer:
MICRON
Quantity:
1 001
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is t
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 17. Bulk Erase (BE) instruction sequence
S
C
D
0
Figure
1
2
Instruction
17.
3
4
5
6
7
AI03752D
BE
) is initiated. While the
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