M25P64-VMF6TP NUMONYX, M25P64-VMF6TP Datasheet - Page 34
M25P64-VMF6TP
Manufacturer Part Number
M25P64-VMF6TP
Description
IC FLASH 64MBIT 50MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P64-VME6TG.pdf
(55 pages)
Specifications of M25P64-VMF6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8M x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P64-VMF6TP
M25P64-VMF6TPTR
M25P64-VMF6TPTR
Available stocks
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Manufacturer
Quantity
Price
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Quantity:
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6.9
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Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see
Figure 16. Sector Erase (SE) instruction sequence
1. Address bit A23 is Don’t Care.
S
C
D
Table
3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
0
Table 2
1
2
Instruction
3
and
4
Figure
5
Table
6
7
16.
3) is not executed.
MSB
23 22
8
9
24 Bit Address
2
29 30 31
1
0
AI03751D
SE
) is