NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 24

• Manufacturer Part Number: NAND01GW3B2CN6E
• Description: IC FLASH 1GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND01GW3B2CN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

Device operations
6.2
Figure 8.
24/61
RB
R
I/O
Setup
Read
Cache read
The cache read operation is used to improve the read throughput by reading data using the
cache register. As soon as the user starts to read one page, the device automatically loads
the next page into the cache register.
A cache read operation consists of three steps (see
1.
2.
3.
The start address must be at the beginning of a page (column address = 00h, see
and
see
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the cache read operation has started, the status register can be read using the Read
Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the cache register is
ready to download new data.
To exit the cache read operation an Exit Cache Read command must be issued (see
Table
If the Exit Cache Read command is issued while the device is internally reading page n+1,
pages n and n+1 will not be output.
Cache read operation
code
00h
Figure
Table
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
Four or five (refer to
address
One bus cycle is required to issue the Cache Read Confirm command to start the
P/E/R controller.
10).
Address
inputs
9). This allows the data to be output uninterrupted after the latency time (t
8.
(Read Busy time)
tBLBH1
Confirm
Cache
Read
code
31h
Table 6
Busy
1st page
and
Table
2nd page
7) bus cycles are then required to input the start
Block N
3rd page
Table 10:
Data output
NAND01G-B2B, NAND02G-B2C
last page
Commands):
Cache
Read
code
Exit
34h
tBLBH4
ai13104b
Table 8
BLBH1
),