NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 30

• Manufacturer Part Number: NAND01GW3B2CN6E
• Description: IC FLASH 1GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND01GW3B2CN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

Device operations
6.6
Figure 14. Block erase operation
6.7
30/61
RB
I/O
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
The operation is initiated on the rising edge of write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
of t
issued, refer to
Block Erase
Setup Code
BLBH4
One bus cycle is required to setup the Block Erase command. Only addresses A18-
A28 (x8) or A17-A27 (x16) are used, the other address inputs are ignored
Two or three bus cycles are then required to load the address of the block to be erased.
Refer to
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
60h
depends on the operation that the device was performing when the command was
Table 8
Table 25: AC characteristics for operations
Block Address
and
Inputs
Table 9
for the block addresses of each device
Confirm
Code
D0h
BLBH4
after the Reset command is issued. The value
(Erase Busy time)
Figure
tBLBH3
Busy
NAND01G-B2B, NAND02G-B2C
14):
for the values.
Read Status Register
70h
SR0
ai07593