MD4832-D512-V3Q18-X/Y SanDisk, MD4832-D512-V3Q18-X/Y Datasheet - Page 52

• Manufacturer Part Number: MD4832-D512-V3Q18-X/Y
• Description: IC MDOC G3 512MB 85-FBGA
• Manufacturer: SanDisk

Specifications of MD4832-D512-V3Q18-X/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 512M (64M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 585-1140

6.4.8 Error Detection/Correction
TrueFFS implements a unique MLC-tailored Error Correction Code (ECC) algorithm to ensure data
reliability. Refer to Section 3.7 for further information on the EDC/ECC mechanism.
6.4.9
In addition to standard storage device functionality, the TrueFFS driver provides extended
functionality. This functionality goes beyond simple data storage capabilities to include features
such as: formatting the media, read/write protection, boot partition(s) access, flash defragmentation
and other options. This unique functionality is available in all TrueFFS-based drivers through the
standard I/O control command of the native file system.
6.4.10 Compatibility
Mobile DiskOnChip G3 requires TrueFFS driver 6.x or higher. Since this driver does not support
other DiskOnChip products, migrating from Mobile DiskOnChip G3 to any other DiskOnChip
product requires changing the TrueFFS driver.
When using different drivers (e.g. TrueFFS SDK, BDK, BIOS extension firmware, etc.) to access
Mobile DiskOnChip G3, verify that all software is based on the same code base version. It is also
important to use only tools (e.g. DFORMAT, DINFO, GETIMAGE, etc.) from the same version as
the firmware and the TrueFFS drivers used in the application. Failure to do so may lead to
unexpected results, such as lost or corrupted data. The driver and firmware version can be verified
by the sign-on messages displayed, or by the version information stored in the driver or tool.
6.5
TrueFFS utilizes an 8KB memory window in the CPU address space, consisting of four 2KB
sections as depicted in Figure 19. When in Reset mode, read cycles from sections 1 and 2 always
return the value 00H to create a fixed and known checksum. When in Normal mode, these two
sections are used for the internal registers. The 2KB Programmable Boot Block is in section 0 and
section 3, to support systems that search for a checksum at the boot stage both from the top and
bottom of memory. The addresses described here are relative to the absolute starting address of the
8KB memory window.
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Special Features Through I/O Control (IOCTL) Mechanism
8KB Memory Window
Preliminary Data Sheet, Rev. 1.1
Mobile DiskOnChip G3
91-SR-011-05-8L