MD4832-D512-V3Q18-X/Y SanDisk, MD4832-D512-V3Q18-X/Y Datasheet - Page 77
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MD4832-D512-V3Q18-X/Y
Manufacturer Part Number
MD4832-D512-V3Q18-X/Y
Description
IC MDOC G3 512MB 85-FBGA
Manufacturer
SanDisk
Datasheet
1.MD4331-D1G-V3Q18-X-PY.pdf
(97 pages)
Specifications of MD4832-D512-V3Q18-X/Y
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
512M (64M x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
585-1140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MD4832-D512-V3Q18-X/Y
Manufacturer:
SanDisk
Quantity:
10 000
9.8
This section discusses hardware design issues for major embedded RISC processor families.
9.8.1
Wait states can be implemented only when Mobile DiskOnChip G3 is designed in a bus that
supports a Wait state insertion, and supplies a WAIT signal.
9.8.2
Mobile DiskOnChip G3 is a Little Endian device. Therefore, byte lane 0 (D[7:0]) is its Least
Significant Byte (LSB) and byte lane 1 (D[15:8]) is its Most Significant Byte (MSB). Within the
byte lanes, bit D0 and bit D8 are the least significant bits of their respective byte lanes. Mobile
DiskOnChip G3 can be connected to a Big Endian device in one of two ways:
1. Make sure to identify byte lane 0 and byte lane 1 of your processor. Then, connect the data bus
2.
9.8.3
The Busy signal (BUSY#) indicates that Mobile DiskOnChip G3 has not yet completed internal
initialization. After reset, BUSY# is asserted while the IPL is downloaded into the internal boot
block and the Data Protection Structures (DPS) are downloaded to the Protection State Machines.
Once the download process is completed, BUSY# is negated. It can be used to delay the first access
to Mobile DiskOnChip G3 until it is ready to accept valid cycles.
Note: The TrueFFS driver does NOT use this signal to indicate that the flash is in busy state (e.g.
9.8.4
Mobile DiskOnChip G3 uses a 16-bit data bus and supports 16-bit data access by default. However,
it can be configured to support 8 or 32-bit data access mode. This section describes the connections
required for each mode.
The default of the TrueFFS driver for Mobile DiskOnChip G3 is set to work in 16-bit mode. It must
be specially configured to support 8 and 32-bit mode. Please see TrueFFS documentation for further
details.
Note: The DiskOnChip data bus must be connected to the Least Significant Bits (LSB) of the
74
so that the byte lanes of the CPU match the byte lanes of Mobile DiskOnChip G3. Pay special
attention to processors that also change the bit ordering within the bytes (for example,
PowerPC). Failing to follow these rules results in improper connection of Mobile DiskOnChip
G3, and prevents the TrueFFS driver from identifying it.
Set the bits SWAPH and SWAPL in the Endian Control register. This enables byte swapping
when used with 16-bit hosts.
program, read, or erase).
system. The system engineer must verify whether the matching host signals are SD[7:0],
SD[15:8] or D[31:24].
Platform-Specific Issues
Wait State
Big and Little Endian Systems
Busy Signal
Working with 8/16/32-Bit Systems
Preliminary Data Sheet, Rev. 1.1
Mobile DiskOnChip G3
91-SR-011-05-8L