EPCS16SI16N Altera, EPCS16SI16N Datasheet - Page 15

• Manufacturer Part Number: EPCS16SI16N
• Description: IC CONFIG DEVICE 16MBIT 16-SOIC
• Manufacturer: Altera
• Series: EPCSr

Specifications of EPCS16SI16N

• Programmable Type: In System Programmable
• Memory Size: 16Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Memory Type: Flash
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1240-5; EPCS16SI16

Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Serial Configuration Device Memory Access
June 2011 Altera Corporation
Operation Codes
Table 3–6. Address Range for Sectors in EPCS4
Table 3–7. Address Range for Sectors in EPCS1
This section describes the operations that can be used to access the memory in serial
configuration devices. The DATA, DCLK, ASDI, and nCS signals access the memory in
serial configuration devices. All serial configuration device operation codes,
addresses and data are shifted in and out of the device serially, with the most
significant bit (MSB) first.
The device samples the active serial data input on the first rising edge of the DCLK after
the active low chip select (nCS) input signal is driven low. Shift the operation code
(MSB first) serially into the serial configuration device through the active serial data
input (ASDI) pin. Each operation code bit is latched into the serial configuration device
on the rising edge of the DCLK.
Different operations require a different sequence of inputs. While executing an
operation, you must shift in the desired operation code, followed by the address
bytes, data bytes, both, or neither. The device must drive nCS high after the last bit of
the operation sequence is shifted in.
operation supported by the serial configuration devices.
For the read byte, read status, and read silicon ID operations, the shifted-in operation
sequence is followed by data shifted out on the DATA pin. You can drive the nCS pin
high after any bit of the data-out sequence is shifted out.
Sector
Sector
7
6
5
4
3
2
1
0
3
2
1
0
Table 3–8
H'70000
H'60000
H'50000
H'40000
H'30000
H'20000
H'10000
H'00000
H'18000
H'10000
H'08000
H'00000
Address Range (Byte Addresses in HEX)
Address Range (Byte Addresses in HEX)
Start
Start
lists the operation sequence for every
Volume 2: Configuration Handbook
H'7FFFF
H'6FFFF
H'5FFFF
H'4FFFF
H'3FFFF
H'2FFFF
H'1FFFF
H'0FFFF
H'1FFFF
H'17FFF
H'0FFFF
H'07FFF
End
End
3–15