PCF8578H/1,118 NXP Semiconductors, PCF8578H/1,118 Datasheet - Page 10

• Manufacturer Part Number: PCF8578H/1,118
• Description: IC LCD DRIVER DOT MATRIX 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8578H/1,118

• Display Type: LCD
• Configuration: Dot Matrix
• Interface: I²C
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935276284118; PCF8578H/1-T; PCF8578H/1-T

NXP Semiconductors
PCF8578_6
Product data sheet
8.2 Power-on reset
8.3 Multiplexed LCD bias generation
V
V
Table 5
to produce the standard multiplex rates.
Table 5.
At power-on the PCF8578 resets to a defined starting condition as follows:
Remark: Do not transfer data on the I
reset action to complete.
The bias levels required to produce maximum contrast depend on the multiplex rate and
the LCD threshold voltage (V
LCD exhibits 10 % contrast.
the discrimination ratios (D) for the different multiplex rates as functions of V
The RMS on-state voltage (V
and the RMS off-state voltage (V
V
Resistors
R1
R2
R3
1. Display blank
2. 1:32 multiplex rate, row mode
3. Start bank 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I
oper
off RMS
on RMS
2
C-bus interface is initialized
=
shows the relative values of the resistors required in the configuration of
V
=
=
DD
Multiplex rates and resistor values for
V
V
–
oper
oper
V
LCD
1
-- -
n
------------------------------ -
2
+
n
------------------------
n
n 1
n
n 1
Rev. 06 — 5 May 2009
–
+
n
–
+
1
1
Table 6
2
th
on(RMS)
Multiplex rate (1:n)
n = 8
R
). V
LCD row/column driver for dot matrix graphic displays
3
off(RMS)
n 2
–
th
–
is typically defined as the RMS voltage at which the
) for the LCD is calculated with the equation
n
shows the optimum voltage bias levels and
2
R
R
C-bus for at least 1 ms after power-on to allow the
) with the equation
Figure 5
n = 16, 24, 32
R
R
n 3
–
R
PCF8578
© NXP B.V. 2009. All rights reserved.
oper
.
Table 7
Figure 5
10 of 46
(1)
(2)
(3)